LM3S600 Datasheet, PDF (171/504 Pages) Bookham, Inc. – Microcontroller

Stellaris^® LM3S600 Microcontroller
Bit/Field
21:14
13
12
11
10
9:6
Name
reserved
PWRDN
OEN
BYPASS
PLLVER
XTAL
Type
RO
R/W
R/W
R/W
R/W
R/W
Reset
0
1
1
1
0
0xB
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL. See Table 5-6 on page 172 for PLL mode control.
PLL Output Enable
This bit specifies whether the PLL output driver is enabled. If cleared,
the driver transmits the PLL clock to the output. Otherwise, the PLL
clock does not oscillate outside the PLL module.
Note: Both PWRDN and OEN must be cleared to run the PLL.
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
See Table 5-4 on page 156 for programming guidelines.
PLL Verification
This bit controls the PLL verification timer function. If set, the verification
timer is enabled and an interrupt is generated if the PLL becomes
inoperative. Otherwise, the verification timer is not enabled.
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below.
Value Crystal Frequency (MHz) Not Crystal Frequency (MHz) Using
Using the PLL
the PLL
0x0
1.000
reserved
0x1
1.8432
reserved
0x2
2.000
reserved
0x3
2.4576
reserved
0x4
3.579545 MHz
0x5
3.6864 MHz
0x6
4 MHz
0x7
4.096 MHz
0x8
4.9152 MHz
0x9
5 MHz
0xA
5.12 MHz
0xB
6 MHz (reset value)
0xC
6.144 MHz
0xD
7.3728 MHz
0xE
8 MHz
0xF
8.192 MHz
July 14, 2014
171
Texas Instruments-Production Data