LM3S600 Datasheet, PDF (156/504 Pages) Bookham, Inc. – Microcontroller

System Control
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Figure 5-4 on page 156 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be individually enabled/disabled.
Figure 5-4. Main Clock Tree
OSC1
OSC2
Main
Osc
1-8 MHz
Internal
Osc
12 MHz
÷4
OSCSRC^a
PLL
(200 MHz
output)
OEN^a
XTAL^a
PWRDN^a
BYPASS^a
USESYSDIV^a
SYSDIV^a
System Clock
a. These are bit fields within the Run-Mode Clock Configuration (RCC) register.
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). Table 5-4 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-3 on page 155.
Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field
SYSDIV
0x0
Divisor
/1
Frequency
(BYPASS=0)
reserved
Frequency (BYPASS=1)
Clock source frequency/2
StellarisWare Parameter^a
SYSCTL_SYSDIV_1^b
0x1
/2 reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x2
/3 reserved
Clock source frequency/3
SYSCTL_SYSDIV_3
0x3
/4 50 MHz
Clock source frequency/4
SYSCTL_SYSDIV_4
0x4
/5 40 MHz
Clock source frequency/5
SYSCTL_SYSDIV_5
0x5
/6 33.33 MHz
Clock source frequency/6
SYSCTL_SYSDIV_6
0x6
/7 28.57 MHz
Clock source frequency/7
SYSCTL_SYSDIV_7
0x7
/8 25 MHz
Clock source frequency/8
SYSCTL_SYSDIV_8
0x8
/9 22.22 MHz
Clock source frequency/9
SYSCTL_SYSDIV_9
0x9
/10 20 MHz
Clock source frequency/10
SYSCTL_SYSDIV_10
0xA
/11 18.18 MHz
Clock source frequency/11
SYSCTL_SYSDIV_11
0xB
/12 16.67 MHz
Clock source frequency/12
SYSCTL_SYSDIV_12
156
July 14, 2014
Texas Instruments-Production Data