TPL5010-Q1 Datasheet, PDF (17/22 Pages) Texas Instruments – AEC-Q100 Nano-Power System Timer with Watchdog Function

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TPL5010-Q1
SNAS679 – SEPTEMBER 2016
10 Power Supply Recommendations
The TPL5010-Q1 requires a voltage supply within 1.8 V and 5.5 V. A multilayer ceramic bypass X7R capacitor of
0.1 μF between VDD and GND pin is recommended.
11 Layout
11.1 Layout Guidelines
The DELAY/M_RST pin is sensitive to parasitic capacitance. It is suggested that the traces connecting the
resistance on this pin to GROUND be kept as short as possible to minimize parasitic capacitance. This
capacitance can affect the initial set up of the time interval. Signal integrity on the WAKE and RSTn pins is also
improved by keeping the trace length between the TPL5010-Q1 and the µC short to reduce the parasitic
capacitance.
11.2 Layout Example
Figure 15. Layout
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