SPNZ187 Datasheet, PDF (17/36 Pages) Texas Instruments – This document describes the known exceptions to the functional specifications for the device.

www.ti.com
CORTEX-R4#61 (ARM ID-720270) — Latched DTR-Full Flags Not Updated Correctly On DTR Access
CORTEX-R4#61 (ARM ID-720270) Latched DTR-Full Flags Not Updated Correctly On DTR Access
Severity
Expected Behavior
Issue
Conditions
Implications
Workaround(s)
Medium
When the debug Data Transfer Register (DTR) is in non-blocking mode, the latched
DTR-full flags (RXfull_l and TXfull_l) record the state of the DTR registers as observed
by the debugger and control the flow of data to and from the debugger to prevent race
hazards. For example, when the target reads data from DBGDTRRXint, the associated
flag RXfull is cleared to indicate that the register has been drained, but the latched value
Rxfull_l remains set. Subsequent debugger writes to DBGDTRRXext are ignored
because RXfull_l is set. RXfull_l is updated from RXfull when the debugger reads
DBGDSCRext such that a debugger write to DBGDTRRXext will only succeed after the
debugger has observed that the register is empty. The ARMv7 debug architecture
requires that RXfull_l be updated when the debugger reads DBGDSCRext and when it
writes DBGDTRRXext. Similarly, TXfull_l must be updated when the debugger reads
DBGDSCRext and when it reads DBGDTRTXext.
Because of this erratum, RXfull_l and TXfull_l are only updated when the debugger
reads DBGDSCRext.
The DTR is in non-blocking mode, that is, DBGDSCR.ExtDCCmode is set to 0b00 and
EITHER:
• The debugger reads DBGDSCRext which shows that RXfull is zero, that is,
DBGDTRRX is empty.
• The debugger writes data to DBGDTRRXext.
• Without first reading the DBGDSCRext, and before the processor has read from
DBGDTRRXint, the debugger performs another write to DBGDTRRXext.
OR
• The debugger reads DBGDSCRext which shows that TXfull is one, that is,
DBGDTRTX is full.
• The debugger reads data from DBGDTRTXext,
• The processor writes new data into DBGDTRTXint,
• Without first reading the DBGDSCRext, the debugger performs another read from
DBGDTRTXext.
The ARMv7 debug architecture requires the debugger to read the DBGDSCRext before
attempting to transfer data via the DTR when in non-blocking mode. This erratum only
has implications for debuggers that violate this requirement. If the erratum occurs via
data transfer, data loss may occur. The architecture requires that data transfer never
occur.
Texas Instruments has verified that TI's Code Composer Studios IDE is not affected by
this issue.
None
SPNZ187 – September 2012
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
RM46x Microcontroller
17