PCM1690-Q1 Datasheet, PDF (17/46 Pages) Texas Instruments – 24-Bit, 192-kHz Sampling, Enhanced Multi-Level ΔΣ,Eight-Channel Audio Digital-to-Analog Converter

PCM1690-Q1
www.ti.com
SBAS551 – JUNE 2011
AUDIO SERIAL PORT OPERATION
The PCM1690-Q1 audio serial port consists of six signals: BCK, LRCK, DIN1, DIN2, DIN3, and DIN4. BCK is a
bit clock input. LRCK is a left/right word clock input or frame synchronization clock input. DIN1/2/3/4 are the
audio data inputs for VOUT1–8.
AUDIO DATA INTERFACE FORMATS AND TIMING
The PCM1690-Q1 supports 10 audio data interface formats: 16-/20-/24-/32-bit I²S, 16-/20-/24-/32-bit left-justified,
24-bit right-justified, 16-bit right-justified, 24-bit left-justified mode DSP, 24-bit I²S mode DSP, 24-bit left-justified
mode TDM, 24-bit I²S mode TDM, 24-bit left-justified mode high-speed TDM, and 24-bit I²S mode high-speed
TDM. In the case of I²S, left-justified, and right-justified data formats, 64 BCKs, 48 BCKs, and 32 BCKs per
LRCK period are supported; but 48 BCKs are limited in 192/384/768 f_S SCKI, and 32 BCKs are limited in 16-bit
right-justified only. In the case of TDM data format in single rate, BCK, LRCK, and DIN1 are used. In the case of
TDM data format in dual rate, BCK, LRCK, and DIN1/2 are used. In the case of high-speed TDM format in dual
rate, BCK, LRCK, and DIN1 are used. In the case of high-speed TDM format in quad rate, BCK, LRCK, and
DIN1/2 are used. TDM format and high-speed TDM format are supported only at SCKI = 512 f_S, 256 f_S, 128 f_S,
and f_BCK ≤ f_SCKI. The audio data formats are selected by MC/SCL/FMT in hardware control mode and by control
register settings in software control mode. All data must be in binary twos complement and MSB first.
Table 5 summarizes the applicable formats and describes the relationships among them and the respective
restrictions with mode control. Figure 22 through Figure 28 show 10 audio interface data formats.
Table 5. Audio Data Interface Formats and Sampling Rate, Bit Clock, and System Clock Restrictions
CONTROL
MODE
Software
control
Hardware
control
FORMAT
I²S/Left-Justified
Right-Justified
I²S/Left-Justified DSP
I²S/ Left-Justified TDM
High-Speed
I²S/Left-Justified TDM
I²S
I²S TDM
DATA BITS
16/20/24/32 ⁽¹⁾
24, 16
24
24
24
24
24
16/20/24/32 ⁽¹⁾
24
24
MAX LRCK
FREQUENCY (f_S)
192 kHz
192 kHz
192 kHz
48 kHz
96 kHz
96 kHz
192 kHz
192 kHz
48 kHz
96 kHz
SCKI RATE (xf_S)
128 to 1152⁽²⁾
128 to 1152⁽²⁾
128 to 768
256, 512
128, 256
256
128
128 to 1152⁽²⁾
512
256
BCK RATE (xf_S)
64, 48
64, 48, 32 (16 bit)⁽³⁾
64
256
128
256
128
64, 48
256
128
APPLICABLE PINS
DIN1/2/3/4
DIN1/2/3/4
DIN1/2/3/4
DIN1
DIN1/2
DIN1
DIN1/2
DIN1/2/3/4
DIN1
DIN1/2
(1) 32-bit data length is acceptable only for BCK = 64 f_S and when using I²S and Left-Justified format.
(2) 1152 f_S is acceptable only for f_S = 32 kHz, BCK = 64 f_S, and when using I²S, Left-Justified, and 24-bit Right-Justified format.
(3) BCK = 32 f_S is supported only for 16-bit data length.
LRCK
Ch 1 (DIN1) or Ch 3 (DIN2)
Ch 5 (DIN3) or Ch 7 (DIN4)
Ch 2 (DIN1) or Ch 4 (DIN2)
Ch 6 (DIN3) or Ch 8 (DIN4)
BCK
DIN1/2/3/4
NM L
MSB
2 10
LSB
NM L
MSB
Figure 22. Audio Data Format: 16-/20-/24-/32-Bit I²S
(N = 15/19/23/31, M = 14/18/22/30, and L = 13/17/21/29)
2 10
LSB
Copyright © 2011, Texas Instruments Incorporated
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