DS99R124AQ Datasheet, PDF (17/26 Pages) Texas Instruments – DS99R124AQ 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

SSC2
L
L
L
L
H
H
H
H
TABLE 3. SSCG Configuration (LFMODE = L) — Des Output
SSC[2:0] Inputs
LFMODE = L (20 - 43 MHz)
SSC1
L
L
H
H
L
L
H
H
SSC0
L
H
L
H
L
H
L
H
fdev (%)
OFF
±0.9
±1.2
±1.9
±2.3
±0.7
±1.3
±1.7
Result
fmod (kHz)
OFF
CLK/2168
CLK/1300
TABLE 4. SSCG Configuration (LFMODE = H) — Des Output
SSC2
L
L
L
L
H
H
H
H
SSC[2:0] Inputs
LFMODE = H (5 - 20 MHz)
SSC1
L
L
H
H
L
L
H
H
SSC0
L
H
L
H
L
H
L
H
fdev (%)
OFF
±0.7
±1.3
±1.8
±2.2
±0.7
±1.2
±1.7
Result
fmod (kHz)
OFF
CLK/625
CLK/385
Stop Stream SLEEP Feature
The Des will enter a low power SLEEP state when the input
serial stream is stopped. A STOP condition is detected when
the embedded clock bits are not present. When the serial
stream starts again, the Des will then lock to the incoming
signal and recover the data. Note – in STOP STREAM
SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
FIGURE 16. SSCG Waveform
30154933
POWER SAVING FEATURES
PowerDown Feature (PDB)
The Des has a PDB input pin to ENABLE or POWER DOWN
the device. This pin can be controlled by the system to save
power, disabling the Des when the display is not needed. An
auto detect mode is also available. In this mode, the PDB pin
is tied High and the Des will enter POWER DOWN when the
serial stream stops. When the serial stream starts up again,
the Des will lock to the input stream and assert the LOCK pin
and output valid data. In POWER DOWN mode, the Data and
PCLK output states are determined by the OSS_SEL status.
Note – in POWER DOWN, the optional Serial Bus Control
Registers are RESET.
Built In Self Test (BIST) — Optional
An optional At-Speed Built In Self Test (BIST) feature sup-
ports the testing of the high-speed serial link. This is useful in
the prototype stage, equipment production, in-system test
and also for system diagnostics. In the BIST mode only an
input clock is required along with control to the Ser and Des
BISTEN input pins. The Ser outputs a test pattern (PRBS7)
and drives the link at speed. The Des detects the PRBS7 pat-
tern and monitors it for errors. The PASS output pin toggles
to flag any payloads that are received with 1 to 24 bit errors.
The BISTM pin selects the operational mode of the PASS pin.
If BISTM = L, the PASS pins reports the final result only. If
BISTM = H, the PASS pins counts payload errors and also
results the result. The result of the test is held on the PASS
output until reset (new BIST test or Power Down). A high on
PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of
the test is controlled by the pulse width applied to the Des
BISTEN pin.
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