DS99R124AQ Datasheet, PDF (15/26 Pages) Texas Instruments – DS99R124AQ 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

Functional Description
The DS99R124AQ receives 24-bits of data over a single se-
rial FPD-Link II pair operating at 140Mbps to 1.2Gbps. The
serial stream also contains an embedded clock, and the DC-
balance information which enhances signal quality and sup-
ports AC coupling. The receiver copnverts the serial stream
into a 4-channel (3 data and 1 clock) FPD-Link LVDS Inter-
face. The device is intended to be used with the
DS90UR241or the DS99R421 FPD-Link II serializers.
The Des converts a single input serial data stream to a FPD-
Link output bus, and also provides a signal check for the
chipset Built In Self Test (BIST) mode. The device can be
configured via external pins or through the optional serial
control bus. The Des features enhance signal quality on the
link by supporting the FPD-Link II data coding that provides
randomization, scrambling, and DC balancing of the data.
The Des includes multiple features to reduce EMI associated
with display data transmission. This includes the randomiza-
tion and scrambling of the data, FPD-Link LVDS Output in-
terface, and also the output spread spectrum clock generation
(SSCG) support. The Des' power saving features include a
power down mode, and optional LVCMOS (1.8 V) interface
compatibility.
The Des can attain lock to a data stream without the use of a
separate reference clock source, which greatly simplifies sys-
tem complexity and overall cost. The Des also synchronizes
to the Ser regardless of the data pattern, delivering true au-
tomatic “plug and lock” performance. It can lock to the incom-
ing serial stream without the need of special training patterns
or sync characters. The Des recovers the clock and data by
extracting the embedded clock information, validating and
then deserializing the incoming data stream.
The DS99R421Q / DS99R124AQ chipset supports 18-bit col-
or depth, HS, VS and DE video control signals and up to three
over-sampled low-speed (general purpose) data bits.
DATA TRANSFER
The DS99R124AQ will receive a pixel of data in the following
format: C1 and C0 represent the embedded clock in the serial
stream. C1 is always HIGH and C0 is always LOW. b[23:0]
contain the scrambled data. DCB is the DC-Balanced control
bit. DCB is used to minimize the short and long-term DC bias
on the signal lines. This bit determines if the data is unmodi-
fied or inverted. DCA is used to validate data integrity in the
embedded data stream. Both DCA and DCB coding schemes
are generated by the Ser and decoded by the Des automati-
cally. Figure 14 illustrates the serial stream per PCLK cycle.
30154937
FIGURE 14. FPD-Link II Serial Stream (DS99R421/DS99R124A)
The device supports clocks in the range of 5 MHz to 43 MHz.
With every clock cycle 24 bits of payload are received along
with the four overhead bits. Thus, the line rate is 1.2 Gbps
maximum (140 Mbps minimum) with an effective data rate of
1.03 Gbps maximum. The link is extremely efficient at 86%
(24/28).
The FPD-Link output will pass along the data to the Display
in the format shown in Figure 15.
30154928
FIGURE 15. FPD-Link Output Format
FPD-LINK II INPUT
Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal ter-
mination. A capacitor may be placed on this pin for additional
common-mode filtering of the differential pair. This can be
useful in high noise environments for additional noise rejec-
tion capability. A 4.7 µF capacitor may be connected to this
pin to Ground.
OUTPUT INTERFACES (LVCMOS & FPD-LINK)
OS[2:0] LVCMOS Outputs
Additional signals maybe received across the serial link per
PCLK. The over-sampled bits are restricted to be low speed
signals and should be less than 1/5 of the frequency of the
PCLK. Signals should convey level information only, as pulse
width distrotion will occur by the over sampling technique and
location of the sampling clock. The three over sampled bits
are exactly mapped to DS99R421's; and to DS90UR421 bits
are: OS0 = DIN21, OS1 = DIN22, and OS2 = DIN23.
CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and
OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to
the serial input, LOCK is Low and the FPD-Link interface state
is determined by the state of the OSS_SEL pin.
After the DS99R124AQ completes its lock sequence to the
input serial data, the LOCK output is driven HIGH, indicating
valid data and clock recovered from the serial input is avail-
able on the FPD-Link outputs. The TxCLK output is held at its
current state at the change from OSC_CLK (if this is enabled
via OSC_SEL) to the recovered clock (or vice versa). Note
that the FPD-Link outputs may be held in an inactive state
(TRI-STATE) through the use of the Output Enable pin (OEN).
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