ADS5444-SP Datasheet, PDF (17/23 Pages) Texas Instruments – CLASS V, 13 BIT, 250 MSPS ANALOG-TO-DIGITAL CONVERTER

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Clock
Source
ADS5444-SP
SGLS391B – MARCH 2008 – REVISED FEBRUARY 2012
0.1 µF
1:4
CLK
MA3X71600LCT−ND
ADS5444
CLK
Figure 17. Differential Clock
For jitter-sensitive applications, the use of a differential clock has some advantages (as with any other ADC) at
the system level. The first advantage is that it allows for common-mode noise rejection at the PCB level.
A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum
ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise
on jitter. See Clocking High Speed Data Converters (SLYT075) for more details.
Figure 17 shows this approach. The back-to-back Schottky diodes can be added to limit the clock amplitude in
cases where this would exceed the absolute maximum ratings, even when using a differential clock.
100 nF
100 nF
499 W
MC100EP16DT
DQ
D
V_BB Q
499 W
50 Ω
100 nF
113 Ω
100 nF
CLK
100 nF ^ADS5444
CLK
50 Ω
Figure 18. Differential Clock Using PECL Logic
Another possibility is the use of a logic-based clock, such as PECL. In this case, the slew rate of the edges is
most likely much higher than the one obtained for the same clock amplitude based on a sinusoidal clock. This
solution would minimize the effect of the slope dependent ADC jitter. Using logic gates to square a sinusoidal
clock may not produce the best results, as logic gates may not have been optimized to act as comparators,
adding too much jitter while squaring the inputs.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1 kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking,
the ADS5444 features good tolerance to clock common-mode variation.
Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty
cycle clock signal should be provided.
Digital Outputs
The ADC provides 13 data outputs (D12 to D0, with D12 being the MSB and D0 the LSB), a data-ready signal
(DRY), and an over-range indicator (OVR) that equals a logic high when the output reaches the full-scale limits.
The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the
ADS5444.
The ADS5444 digital outputs are LVDS compatible.
Copyright © 2008–2012, Texas Instruments Incorporated
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