ADS5444-SP Datasheet, PDF (11/23 Pages) Texas Instruments – CLASS V, 13 BIT, 250 MSPS ANALOG-TO-DIGITAL CONVERTER

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1000.00
ADS5444-SP
SGLS391B – MARCH 2008 – REVISED FEBRUARY 2012
100.00
10.00
Electromigration Fail Mode
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1.00
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Continuous Tj (°C)
Figure 2. ADS5444 Estimated Device Life at Elevated Temperatures Electromigration Fail Mode
DEFINITION OF SPECIFICATIONS
Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low frequency value.
Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs.
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine wave clock results in a 50% duty cycle.
Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1
LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSB.
Integral Nonlinearity (INL) The INL is the deviation of the ADCs transfer function from a best fit line determined
by a least squares curve fit of that transfer function. The INL at each analog input value is the difference
between the actual transfer function and this best fit line, measured in units of LSB.
Gain Error The gain error is the deviation of the ADCs actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range.
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