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TMS320F280049 Datasheet, PDF (160/217 Pages) Texas Instruments – Piccolo Microcontrollers
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TMS320F280049, TMS320F280049C, TMS320F280049M
TMS320F280048, TMS320F280048C, TMS320F280045
TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C
SPRS945A – JANUARY 2017 – REVISED AUGUST 2017
www.ti.com
5.11.5.1.1 Non-High-Speed Master Mode Timings
Table 5-73 lists the SPI master mode switching characteristics where the clock phase = 0. Figure 5-66
shows the SPI master mode external timing where the clock phase = 0.
Table 5-74 lists the SPI master mode switching characteristics where the clock phase = 1. Figure 5-67
shows the SPI master mode external timing where the clock phase = 1.
Table 5-75 lists the SPI master mode timing requirements.
Table 5-73. SPI Master Mode Switching Characteristics (Clock Phase = 0)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
(BRR + 1)
CONDITION (1)
MIN
MAX UNIT
1 tc(SPC)M
2 tw(SPC1)M
3 tw(SPC2)M
4 td(SIMO)M
Cycle time, SPICLK
Pulse duration, SPICLK, first pulse
Pulse duration, SPICLK, second
pulse
Delay time, SPICLK to SPISIMO
valid
Even
Odd
Even
Odd
Even
Odd
Even, Odd
4tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M – 3
0.5tc(SPC)M +
0.5tc(LSPCLK) – 3
0.5tc(SPC)M – 3
0.5tc(SPC)M –
0.5tc(LSPCLK) – 3
128tc(LSPCLK)
ns
127tc(LSPCLK)
0.5tc(SPC)M + 3
0.5tc(SPC)M + ns
0.5tc(LSPCLK) + 3
0.5tc(SPC)M + 3
0.5tc(SPC)M – ns
0.5tc(LSPCLK) + 3
5 ns
5 tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
Even
Odd
0.5tc(SPC)M – 3
0.5tc(SPC)M –
0.5tc(LSPCLK) – 3
ns
Even
0.5tc(SPC)M – 3
23 td(SPC)M
Delay time, SPISTE valid to SPICLK
Odd
0.5tc(SPC)M –
0.5tc(LSPCLK) – 3
ns
24 td(STE)M
Delay time, SPICLK to SPISTE
invalid
Even
Odd
0.5tc(SPC)M – 3
0.5tc(SPC)M –
0.5tc(LSPCLK) – 3
ns
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
160 Specifications
Copyright © 2017, Texas Instruments Incorporated
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