TMS320DM6435_16 Datasheet, PDF (160/252 Pages) Texas Instruments – Digital Media Processor

TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
6.7 Clock PLLs
There are two independently controlled PLLs on DM6435. PLL1 generates the frequencies required for the
DSP, DMA, VPFE, and other peripherals. PLL2 generates the frequencies required for the DDR2
interface. The recommended reference clock for both PLLs is the 27-MHz crystal input.
6.7.1 PLL1 and PLL2
Both PLL1 and PLL2 power is supplied externally via the 1.8 V PLL power-supply pin (PLL_PWR18). An
external EMI filter circuit must be added to PLL_PWR18, as shown in Figure 6-11. The 1.8-V supply of the
EMI filter must be from the same 1.8-V power plane supplying the device’s 1.8-V I/O power-supply pins
(DV_DDDR2). TI recommends EMI filter manufacturer Murata, part number NFM18CC222R1C3.
All PLL external components (C1, C2, and the EMI Filter) must be placed as close to the device as
possible. For the best performance, TI recommends that all the PLL external components be on a single
side of the board without jumpers, switches, or components other than the ones shown in Figure 6-11. For
reduced PLL jitter, maximize the spacing between switching signals and the PLL external components
(C1, C2, and the EMI Filter).
DM643x
+1.8 V
EMI Filter
C1
0.1 mF
C2
0.01 mF
PLL_PWR18
PLL1
PLL2
Figure 6-11. PLL1 and PLL2 External Connection
The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements,
see Section 6.7.4, Clock PLL Electrical Data/Timing (Input and Output Clocks).
There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating
frequency for MXI/CLKIN, PLLOUT, and the device clocks (SYSCLKs). The PLL Controllers must be
configured not to exceed any of these constraints documented in this section (certain combinations of
external clock inputs, internal dividers, and PLL multiply ratios might not be supported). For these
constraints (ranges), see Table 6-14 through Table 6-16.
Table 6-14. PLL1 and PLL2 Multiplier Ranges
PLL MULTIPLIER (PLLM)
MIN
PLL1 Multiplier
x14
PLL2 Multiplier
x14
MAX
x30
x32
160 Peripheral Information and Electrical Specifications
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