TMS320DM6435_16 Datasheet, PDF (117/252 Pages) Texas Instruments – Digital Media Processor

www.ti.com
TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
Table 3-47. EMIFA/VPSS Sub-Block 0 Pin-By-Pin Mux Control
SIGNAL NAME
PCLK/GP[54]
YI7(CCD7)/GP[43]
YI6(CCD6)/GP[42]
YI5(CCD5)/GP[41]
YI4(CCD4)/GP[40]
YI3(CCD3)/GP[39]
YI2(CCD2)/GP[38]
YI1(CCD1)/GP[37]
YI0(CCD0)/GP[36]
VD/GP[53]
HD/GP[52]
CI7(CCD15)/EM_A[13]/GP[51]
CI6(CCD14)/EM_A[14]/GP[50]
CI5(CCD13)/EM_A[15]/GP[49]
CI4(CCD12)/EM_A[16]/GP[48]
CI3(CCD11)/EM_A[17]/GP[47]
CI2(CCD10)/EM_A[18]/GP[46]
CI1(CCD9)/EM_A[19]/GP[45]
CI0(CCD8)/EM_A[20]/GP[44]
C_WE/EM_R/W/GP[35]
C_FIELD/EM_A[21]/GP[34]
VPFE
FUNCTION
SELECT
PCLK
CCDCSEL = 1
YI7(CCD7)
YI6(CCD6)
YI5(CCD5)
YI4(CCD4)
YI3(CCD3)
YI2(CCD2)
YI1(CCD1)
YI0(CCD0)
VD
HVDSEL = 1
HD
CI7(CCD15)
CI6(CCD14)
AEM = 0/1/5,
AEAW = 0,
CI76SEL = 1
CI5(CCD13)
CI4(CCD12)
AEM = 0/1/5,
AEAW = 0/1⁽¹⁾,
CI54SEL = 1
CI3(CCD11)
CI2(CCD10)
AEM = 0/1/5,
AEAW = 0/1/2⁽¹⁾,
CI32SEL = 1
CI1(CCD9)
CI0(CCD8)
AEM = 0/1/5,
AEAW = 0/1/2/3⁽¹⁾,
CI10SEL = 1
C_WE
CWENSEL = 1,
AEM = 0/5
C_FIELD
CFLDSEL = 1,
AEM = 0/1/5
MULTIPLEXED FUNCTIONS
EMIFA ADDR/CTRL
FUNCTION
SELECT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
EM_A[13]
EM_A[14]
AEM = 1,
AEAW = 1/2/3/4,
CI76SEL = 0
EM_A[15]
EM_A[16]
AEM = 1,
AEAW = 2/3/4,
CI54SEL = 0
EM_A[17]
EM_A[18]
AEM = 1,
AEAW = 3/4,
CI32SEL = 0
EM_A[19]
EM_A[20]
AEM = 1,
AEAW = 4,
CI10SEL = 0
EM_R/W
CWENSEL = 0,
AEM = 1
EM_A[21]
CFLDSEL = 0,
AEM = 1
GPIO
FUNCTION
SELECT
GP[54]
CCDCSEL = 0
GP[43]
GP[42]
GP[41]
GP[40]
GP[39]
GP[38]
GP[37]
GP[36]
GP[53]
HVDSEL = 0
GP[52]
GP[51]
GP[50]
AEM = 0/1/5,
AEAW = 0,
CI76SEL = 0
GP[49]
GP[48]
AEM = 0/1/5,
AEAW = 0/1⁽¹⁾,
CI54SEL = 0
GP[47]
GP[46]
AEM = 0/1/5,
AEAW = 0/1/2⁽¹⁾,
CI32SEL = 0
GP[45]
GP[44]
AEM = 0/1/5,
AEAW = 0/1/2/3⁽¹⁾,
CI10SEL = 0
GP[35]
CWENSEL = 0,
AEM = 0/5
GP[34]
CFLDSEL = 0,
AEM = 0/5
(1) AEAW = 1/2/3/4 is only valid if AEM[2:0] = 1.
Submit Documentation Feedback
Device Configuration 117