VCE6467T_15 Datasheet, PDF (16/353 Pages) Texas Instruments – Digital Media System-on-Chip

VCE6467T, AVCE6467T
SPRS690 – MARCH 2011
www.ti.com
2.4.2 DSP Memory Mapping
The DSP memory map is shown in Section 2.6, Memory Map Summary. Configuration of the control
registers for DDR2, EMIFA, and ARM Internal RAM is supported by the ARM. The DSP has access to
memories shown in the following sections.
2.4.2.1 ARM Internal Memories
The DSP has access to the 32KB ARM Internal RAM on the ARM D-TCM interface (i.e., data only).
2.4.2.2 External Memories
The DSP has access to the following External memories:
• DDR2 Synchronous DRAM
• Asynchronous EMIF / NOR Flash
• ATA
2.4.2.3 DSP Internal Memories
The DSP has access to the following DSP memories:
• L2 RAM
• L1P RAM
• L1D RAM
2.4.2.4 C64x+ CPU
The C64x+ core uses a two-level cache-based architecture. The Level 1 Program memory/cache (L1P)
consists of 32 KB memory space that can be configured as mapped memory or direct mapped cache. The
Level 1 Data memory/cache (L1D) consists of 32 KB that can be configured as mapped memory or 2-way
set associated cache. The Level 2 memory/cache (L2) consists of a 128 KB RAM memory space that is
shared between program and data space. L2 memory can be configured as mapped memory, cache, or a
combination of both.
Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device.
HEX ADDRESS RANGE
0x0184 0000
0x0184 0020
0x0184 0024
0x0184 0040
0x0184 0044
0x0184 0048 - 0x0184 0FFC
0x0184 1000
0x0184 1004 - 0x0184 1FFC
0x0184 2000
0x0184 2004
0x0184 2008
0x0184 200C
0x0184 2010 - 0x0184 3FFF
0x0184 4000
0x0184 4004
0x0184 4010
0x0184 4014
0x0184 4018
Table 2-2. C64x+ Cache Registers
REGISTER ACRONYM
L2CFG
L1PCFG
L1PCC
L1DCFG
L1DCC
-
EDMAWEIGHT
-
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
-
L2WBAR
L2WWC
L2WIBAR
L2WIWC
L2IBAR
DESCRIPTION
L2 Cache configuration register
L1P Size Cache configuration register
L1P Freeze Mode Cache configuration register
L1D Size Cache configuration register
L1D Freeze Mode Cache configuration register
Reserved
L2 EDMA access control register
Reserved
L2 allocation register 0
L2 allocation register 1
L2 allocation register 2
L2 allocation register 3
Reserved
L2 writeback base address register
L2 writeback word count register
L2 writeback invalidate base address register
L2 writeback invalidate word count register
L2 invalidate base address register
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Device Overview
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