VCE6467T_15 Datasheet, PDF (158/353 Pages) Texas Instruments – Digital Media System-on-Chip

VCE6467T, AVCE6467T
SPRS690 – MARCH 2011
www.ti.com
6.5.3 Clock PLL Considerations With External Clock Sources
If the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power
both the VCE6467T device and the external clock oscillator circuit. The minimum CLKIN rise and fall times
should also be observed. For the input clock timing requirements, see Section 6.5.5, Clock PLL Electrical
Data/Timing (Input and Output Clocks).
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock
source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Temperature, and Section 6.5.5, Clock
PLL Electrical Data/Timing (Input and Output Clocks).)
6.5.4 Output Clocks (CLKOUT0, AUDIO_CLK1, AUDIO_CLK0) - Clock Select Logic
The VCE6467T includes a selectable general-purpose clock output (CLKOUT0) [see Figure 6-12] and two
selectable audio output clocks (AUDIO_CLK0 and AUDIO_CLK1) for synchronizing external audio devices
with the on-chip system or video clocks [see Figure 6-13 and Figure 6-14]. The source for these output
clocks is controlled by the CLKCTL register (0x01C4 005C). For more detailed information on the CLKCTL
register, see Section 3.3.3, Clock and Oscillator Control.
CLKCTL.CLKOUT
AUX_MXI/AUX_CLKIN
DEV_MXI/DEV_CLKIN
AUX_MXI
1010
PLLDIV9 (/6 Prog)
PLLDIV8 (/8 Prog)
PLLDIV6 (/8 Prog)
PLLDIV5 (/8 Prog)
PLLDIV4 (/6 Prog)
PLLDIV3 (/4 Fixed)
PLL Controller 1
SYSCLK9
SYSCLK8
SYSCLK6
SYSCLK5
SYSCLK4
SYSCLK3
AUXCLK
1001
1000
0110
0101
0100
0011
0001
0000
CLKOUT0
Figure 6-12. CLKOUT0 Source Selection
158 Peripheral Information and Electrical Specifications
Copyright © 2011, Texas Instruments Incorporated
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