TUSB1210-Q1 Datasheet, PDF (16/66 Pages) Texas Instruments – TUSB1210-Q1 Standalone USB Transceiver Chip Silicon

TUSB1210-Q1
SLLSEL4A – SEPTEMBER 2014 – REVISED OCTOBER 2014
Feature Description (continued)
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NOTE
LS device mode is not allowed by a USB2.0 HS capable PHY, therefore it is not supported
by TUSB1210-Q1. This is stated in USB2.0 standard Chapter 7, page 119, second
paragraph: “A high-speed capable upstream facing transceiver must not support low-
speed signaling mode..” There is also some related commentary in Chapter 7.1.2.3.
7.3.1.2.1 PHY Electrical Characteristics
The PHY is the physical signaling layer of the USB 2.0. It essentially contains all the drivers and receivers
required for physical data and protocol signaling on the DP and DM lines.
The PHY interfaces to the USB controller through a standard 12-pin digital interface called UTMI+ low pin
interface (ULPI).
The transmitters and receivers inside the PHY are classified into two main classes.
• The full-speed (FS) and low-speed (LS) transceivers. These are the legacy USB1.x transceivers.
• The HS (HS) transceivers
In order to bias the transistors and run the logic, the PHY also contains reference generation circuitry which
consists of:
• A DPLL which does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for USB and
also the clock required for the switched capacitor resistance block.
• A switched capacitor resistance block which is used to replicate an external resistor on chip.
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
Apart from this, the PHY also contains circuitry which protects it from accidental 5-V short on the DP and DM
lines.
7.3.1.2.1.1 LS/FS Single-Ended Receivers
In addition to the differential receiver, there is a single-ended receiver (SE–, SE+) for each of the two data lines
D+/–. The main purpose of the single-ended receivers is to qualify the D+ and D– signals in the full-speed/low-
speed modes of operation. See PHY Electrical Characteristics.
7.3.1.2.1.2 LS/FS Differential Receiver
A differential input receiver (Rx) retrieves the LS/FS differential data signaling. The differential voltage on the line
is converted into digital data by a differential comparator on DP/DM. This data is then sent to a clock and data
recovery circuit which recovers the clock from the data. An additional serial mode exists in which the differential
data is directly output on the RXRCV pin. See Switching Characteristics.
7.3.1.2.1.3 LS/FS Transmitter
The USB transceiver (Tx) uses a differential output driver to drive the USB data signal D+/– onto the USB cable.
The driver's outputs support 3-state operation to achieve bidirectional half-duplex transactions. See Switching
Characteristics.
7.3.1.2.1.4 HS Differential Receiver
The HS receiver consists of the following blocks:
A differential input comparator to receive the serial data
• A squelch detector to qualify the received data
• An oversampler-based clock data recovery scheme followed by a NRZI decoder, bit unstuffing, and serial-to-
parallel converter to generate the ULPI DATAOUT
See Switching Characteristics.
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