TLC4545ID Datasheet, PDF (16/26 Pages) Texas Instruments – 5-V, LOW POWER, 16-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

TLC4541, TLC4545
SLAS293 − DECEMBER 2001
PRINCIPLES OF OPERATION
SCLK
1
2
8
9
1
2
8
9
1
2
th7
tsu7
th7
tsu6
CS
tcyc(reset)
OR
tcyc(reset)
Normal Cycle Begins
FS
SDO
Initialization Cycle (Reset)
ÎÎÎÎÎÎMSB
ÎÎÎÎÎÎ^MSB
ÎÎÎÎ^{MSB MSB−1}
Figure 21. Critical Timing: Initialization Cycle (TLC4541 Only)
detailed description
The TLC4541/5 are successive approximation (SAR) ADCs utilizing a charge-redistribution DAC. Figure 22
shows a simplified version of the ADC. The sampling capacitor acquires the signal on AIN (or the AIN(+) pin for
TLC4545) during the sampling period. When the conversion process starts, the SAR control logic and charge
redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the
comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the
ADC output code is generated.
Charge
Redistribution
DAC
AIN/
AIN(+)
−
Control
Ci
+
Logic
Ci
GND/
AIN(−)
Figure 22. Simplified SAR Circuit
ADC Code
16
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