TLC4545ID Datasheet, PDF (14/26 Pages) Texas Instruments – 5-V, LOW POWER, 16-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN

TLC4541, TLC4545
SLAS293 − DECEMBER 2001
PRINCIPLES OF OPERATION
control via pin 1 (CS, DSP interface)
All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the
CS input of the ADC. A falling edge on the CS input while SCLK is high or low initiates the cycle. (For TLC4541
in this configuration, the FS input is tied to V_DD.) Enough time should be allowed before the next rising CS edge
so that the conversion cycle is not terminated prematurely.
1
2
3
4
5
6
7
12 13
14 15 16
24
1
SCLK
ts
CS
The CS Input Signal is
SDO Data is the Result of the Previous Sample
Generated by the FS Output _{For TLC45xx, the LSB is Presented on the Rising SCLK 16th Edge}
From a TMS320 DSP
SDO
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
LSB−4 LSB−3 LSB−2 LSB−1 LSB
tconv
t(PWRDWN)
Figure 16. DSP Cycle Timing Using the CS Input (FS = 1 for TLC4541 Only)
MSB MSB−1
control via pin 1 and pin 7 (CS and FS or FS only, DSP interface)
Only TLC4541 is compatible with this mode of operation. The CS input to the ADC can be controlled via a
general-purpose I/O pin from the DSP or tied to ground. The FS signal from the DSP is connected directly to
the FS input of the ADC. A rising FS edge releases the MSB to the SDO output. The falling edge on the FS input
while SCLK is high or low initiates the cycle. The CS input should remain low for the entire sampling time plus
4 SCLK decoding time after falling FS (24 falling SCLK edges) and can then be released at any time during the
remainder of the conversion cycle. The optimum DSP interface is achieved when tying CS to ground and using
only the FS input to control the ADC.
SCLK
1
2
3
4
5
6
14 15 16 17 ²⁴
12
3
4
CS
FS
SDO
ts
SDO Data is the Result of the Previous Sample
ÎÎFor TLC45xx, the LSB is Presented on the Rising SCLK 16th Edge
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 LSB−3 LSB−2 LSB−1 LSB
The MSB is Presented on the SDO Output After
a Rising Edge on the FS Input.
tconv
t(PWRDWN)
ÎÎ^{MSB MSB−1 MSB−2 MSB−3}
The Device Will go into the Power Down State After the Conversion is
Complete. A Falling CS Edge or Rising FS Edge, Whichever Occurs First,
Removes the Device From Power Down.
Figure 17. DSP Cycle Timing Using FS Only (or Using Both CS and FS for the TLC4541)
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