LP38852-ADJ Datasheet, PDF (16/31 Pages) Texas Instruments – 1.5-A Fast-Response High-Accuracy Adjustable LDO Linear Regulator

LP38852-ADJ
SNVS482F – JANUARY 2007 – REVISED DECEMBER 2015
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8.2.2.1.2 Output Capacitor
A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can
be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the device
and returned to the device ground pin with a clean analog ground.
Only high-quality ceramic types such as X5R or X7R are recommended, as the Z5U and Y5F types do not
provide sufficient capacitance over temperature.
Tantalum capacitors also provide stable operation across the entire operating temperature range. However, the
effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum
recommended 10-µF ceramic capacitor at the output allows unlimited capacitance, tantalum or aluminum, to be
added in parallel.
8.2.2.1.3 Bias Capacitor
The capacitor on the bias pin must be at least 1 µF and can be any good-quality capacitor (ceramic is
recommended).
8.2.2.1.4 Setting the Output Voltage
According to Table 1, R1 is set to 1.07 kΩ, and R2 is set to 1.78 kΩ.
8.2.2.1.5 Feed Forward Capacitor, C_FF
When using a ceramic capacitor for C_OUT, the typical ESR value is too small to provide any meaningful positive
phase compensation, F_Z, to offset the internal negative phase shifts in the gain loop (see Figure 23).
F_Z = (1 / (2 × π x C_OUT × ESR) )
(4)
A capacitor placed across the gain resistor R1 provides additional phase margin to improve load transient
response of the device. This capacitor, C_FF, in parallel with R1, forms a zero in the loop response given by the
formula:
F_Z = (1 / (2 × π x C_FF × R1) )
(5)
For optimum load transient response select C_FF so the zero frequency, F_Z, falls between 10 kHz and 15 kHz.
(C_FF = (1 / (2 × π x R1 × F_Z)
(6)
The phase lead provided by C_FF diminishes as the DC gain approaches unity, or V_OUT approaches V_ADJ. This is
because C_FF also forms a pole with a frequency of:
F_P = (1 / (2 x π × C_FF × (R1 || R2) ) )
(7)
NOTE
It is important that at higher output voltages, where R1 is much larger than R2, the pole
and zero are far apart in frequency. At lower output voltages the frequency of the pole and
the zero move closer together. The phase lead provided from C_FF diminishes quickly as
the output voltage is reduced and has no effect when V_OUT = V_ADJ. For this reason, relying
on this compensation technique alone is adequate only for higher output voltages. For the
LP38852-ADJ, the practical minimum V_OUT is 0.8 V when a ceramic capacitor is used for
C_OUT.
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