DS99R101_14 Datasheet, PDF (16/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101, DS99R102
SNLS240D – MARCH 2007 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
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The DS99R101 Serializer and DS99R102 Deserializer chipset is an easy-to-use transmitter and receiver pair that
sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 72 Mbps to 960 Mbps throughput.
The DS99R101 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS serial data stream
with embedded clock. The DS99R102 receives the LVDS serial data stream and converts it back into a 24-bit
wide parallel data and recovered clock. The 24-bit Serializer/Deserializer chipset is designed to transmit data
over shielded twisted pair (STP) at clock speeds from 3 MHz to 40 MHz.
The Deserializer can attain lock to a data stream without the use of a separate reference clock source. The
Deserializer synchronizes to the Serializer regardless of data pattern, delivering true automatic “plug and lock”
performance. The Deserializer recovers the clock and data by extracting the embedded clock information and
validating data integrity from the incoming data stream and then deserializes the data. The Deserializer monitors
the incoming clock information, determines lock status, and asserts the LOCK output high when lock occurs.
Each has a power down control to enable efficient operation in various applications.
INITIALIZATION AND LOCKING MECHANISM
Initialization of the DS99R101 and DS99R102 must be established before each device sends or receives data.
Initialization refers to synchronizing the Serializer’s and Deserializer’s PLL’s together. After the Serializers locks
to the input clock source, the Deserializer synchronizes to the Serializers as the second and final initialization
step.
Step 1: When V_DD is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE
and internal circuitry is disabled by on-chip power-on circuitry. When V_DD reaches V_DD OK (2.2V) the PLL in
Serializer begins locking to a clock input. For the Serializer, the local clock is the transmit clock, TCLK. The
Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the Serializer
block is now ready to send data patterns. The Deserializer output will remain in TRI-STATE while its PLL locks to
the embedded clock information in serial data stream. Also, the Deserializer LOCK output will remain low until its
PLL locks to incoming data and sync-pattern on the RIN± pins.
Step 2: The Deserializer PLL acquires lock to a data stream without requiring the Serializer to send special
patterns. The Serializer that is generating the stream to the Deserializer will automatically send random (non-
repetitive) data patterns during this step of the Initialization State. The Deserializer will lock onto embedded clock
within the specified amount of time. An embedded clock and data recovery (CDR) circuit locks to the incoming bit
stream to recover the high-speed receive bit clock and re-time incoming data. The CDR circuit expects a coded
input bit stream. In order for the Deserializer to lock to a random data stream from the Serializer, it performs a
series of operations to identify the rising clock edge and validates data integrity, then locks to it. Because this
locking procedure is independent on the data pattern, total random locking duration may vary. At the point when
the Deserializer’s CDR locks to the embedded clock, the LOCK pin goes high and valid RCLK/data appears on
the outputs. Note that the LOCK signal is synchronous to valid data appearing on the outputs. The Deserializer’s
LOCK pin is a convenient way to ensure data integrity is achieved on receiver side.
DATA TRANSFER
After lock is established, the Serializer inputs DIN0–DIN23 are used to input data to the Serializer. Data is
clocked into the Serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable via the
TRFB pin. TRFB high selects the rising edge for clocking data and low selects the falling edge. The Serializer
outputs (DOUT±) are intended to drive point-to-point connections or limited multi-point applications.
CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream. The CLK1
bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded clock bits
in the serial stream. DCB functions as the DC Balance control bit. It does not require any pre-coding of data on
transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal lines. This
bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used to validate data
integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and automatically
performed within Serializer and Deserializer.
The chipset supports clock frequency ranges of 3 MHz to 40 MHz. Every clock cycle, 24 databits are sent along
with 4 additional overhead control bits. Thus the line rate is 1.12 Gbps maximum (84 Mbps minimum). The link is
extremely efficient at 86% (24/28). Twenty five (24 data + 1 clock) plus associated ground signals are reduced to
only 1 single LVDS pair providing a compression ratio of better then 25 to 1.
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