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| DS99R101_14 Datasheet, PDF (10/30 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer | |||
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DS99R101, DS99R102
SNLS240D â MARCH 2007 â REVISED APRIL 2013
REN
500:
VREF
CL = 8pF
+
-
VREF = VDD/2 for tZLR or tLZR,
VREF = 0V for tZHR or tHZR
www.ti.com
VOH
REN
VOL
VDD/2
tLZR
VDD/2
tZLR
VOL
ROUT [23:0]
VOH
tHZR
VOL + 0.5V
tZHR
VOL + 0.5V
VOH - 0.5V
VOH + 0.5V
Note: CL includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0]
Figure 13. Deserializer TRI-STATE Test Circuit and Timing
2.0V
PWDN
RIN±
tDRDL
0.8V
}v[Å¡ Å
LOCK TRI-STATE
ROUT [0:23]
TRI-STATE
TRI-STATE
tHZR or tLZR
TRI-STATE
RCLK
TRI-STATE
TRI-STATE
REN
Figure 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
10
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Copyright © 2007â2013, Texas Instruments Incorporated
Product Folder Links: DS99R101 DS99R102
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