BQ24702_16 Datasheet, PDF (16/37 Pages) Texas Instruments – MULTICHEMISTRY BATTERY CHARGER CONTROLLER

bq24702
bq24703
SLUS553E – MAY 2003 – REVISED OCTOBER 2007
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ZERO VOLT OPERATING
The zero volt operation is intended to provide a low current path to close open packs and protect the system in
the event of a pack cell short-circuit condition or if a short is applied to the pack terminal. It is not designed to
precharge depleted packs, as it is disabled at voltages that are not within normal pack operating range for
precharge.
If the voltage at BATDEP pin is below the zero volt operation threshold , charge is enabled (EN=HI), and ac is
selected (ACSEL=HI) the bq24702/3 enters the zero volt operation mode. When the zero volt operation mode is
on, the internal PWM is disabled, and an internal power MOSFET connects SRP to V_CC. The battery charge
current is limited by the filter resistor connected to SRP pin (R19). R19 must be dimensioned to withstand the
worst case power dissipation when in zero volt operation mode.
The zero volt operation mode is disabled when BATDEP is above the zero volt operation threshold, and the main
PWM loop is turned on if charge is enabled, regulating the current to the value set by SRSET voltage. To avoid
errors on the charge current both resistors on the SRP, SRN filter must have the same value. Note, however,
that R21 (connected to SRN) does not dissipate any power when in zero volt operation and can be of minimum
size.
PWM OPERATION
The three open collector g_m amplifiers are tied to the COMP pin (refer to Figure 2), which is internally biased up
by a 100-μA constant current source. The voltage on the COMP pin is the control voltage (V_C) for the PWM
comparator. The PWM comparator compares V_C to the sawtooth ramp of the internally fixed 300-kHz oscillator to
provide duty cycle information for the PWM drive. The PWM drive is level-shifted to provide adequate gate
voltage levels for the external P-channel MOSFET. Refer to PWM selector switch gate drive section for gate
drive voltage levels.
Q1
+
I_SW
SW
V_ADPT
D1
V_BAT
COMP
10
Z_COMP
CLK
OSC
RAMP
5V
100 µA
ENABLE
LATCH OUT
SQ
RQ
PWM COMPARATOR
FROM ENABLE LOGIC
LEVEL
SHIFT
VCC
PWM
DRIVE
VHSP
21
PWM
ENABLE
+
BATTERY
VOLTAGE
BATTERY CHARGE
CURRENT
ADP CURRENT
gm
AMPLIFIERS
+
1.25 V
13
BATP
Figure 2. PWM Controller Block Diagram
UDG-00114
16
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