BQ24040_16 Datasheet, PDF (16/38 Pages) Texas Instruments – Single Cell Li-Ion and Li-Pol Battery Charger With Auto Start

bq24040, bq24041, bq24045
SLUS941F – SEPTEMBER 2009 – REVISED MARCH 2015
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Feature Description (continued)
8.3.6 Power Good Indication (PG)
After application of a 5V source, the input voltage rises above the UVLO and sleep thresholds (V_IN>V_BAT+V_DT),
but is less than OVP (V_IN<V_OVP,), then the PG FET turns on and provides a low impedance path to ground. See
Figure 20, Figure 21, and Figure 33.
8.3.7 CHG Terminal Indication
The charge terminal has an internal open drain FET which is on (pulls down to V_SS) during the first charge only
(independent of TTDM) and is turned off once the battery reaches voltage regulation and the charge current
tapers to the termination threshold set by the PRE-TERM resistor. The bq24041 does not terminate charge,
however, the CHG terminal will turn off once the battery current reaches 10% of the programmed charge current.
The charge terminal is high impedance in sleep mode and OVP (if PG is high impedance) and return to its
previous state once the condition is removed.
Cycling input power, pulling the TS terminal low and releasing or entering pre-charge mode causes the CHG
terminal to go reset (go low if power is good and a discharged battery is attached) and is considered the start of
a first charge.
8.4 Device Functional Modes
8.4.1 CHG and PG LED Pull-up Source
For host monitoring, a pull-up resistor is used between the "STATUS" terminal and the V_CC of the host and for a
visual indication a resistor in series with an LED is connected between the "STATUS" terminal and a power
source. If the CHG or PG source is capable of exceeding 7V, a 6.2V zener should be used to clamp the voltage.
If the source is the OUT terminal, note that as the battery changes voltage, and the brightness of the LEDs vary.
Charging State
1st Charge after VIN applied
Refresh Charge
OVP
SLEEP
TEMP FAULT
CHG FET/LED
ON
OFF
ON for 1st Charge
V_IN Power Good State
UVLO
PG FET/LED
SLEEP Mode
OFF
OVP Mode
Normal Input (V_OUT + V_DT < V_IN <
V_OUP)
ON
PG is independent of chip disable
8.4.2 Auto Start-up (bq24041)
The auto start-up feature is an OR gate with two inputs; an internal power good signal (logic 1 when V_IN>V_BAT +
V_IN-DT) and an external input from ASI terminal (internal 100k pull-down). The ASO terminal outputs a signal that
can be used as a system boot signal. The OR gate is powered by the OUT terminal and the OUT terminal must
be powered by an external source (battery or P/S) or via the IN terminal for the ASO terminal to deliver a logic
High. The ASI and/or the internal power good signal have to be logic high for the ASO to be logic high. The
ASI/ASO, OUT and PG signals are used in production testing to test the system without a battery.
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