BQ24040_16 Datasheet, PDF(13/38 Page) Texas Instruments – Single Cell Li-Ion and Li-Pol Battery Charger With Auto Start

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BQ24040_16 Datasheet, PDF (13/38 Pages) Texas Instruments – Single Cell Li-Ion and Li-Pol Battery Charger With Auto Start

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Functional Block Diagram (continued)

bq24040, bq24041, bq24045

SLUS941F â SEPTEMBER 2009 â REVISED MARCH 2015

VO(REG)

IO(OUT)

FAST-CHARGE

CURRENT

PRE-CHARGE

CURRENT AND

TERMINATION

THRESHOLD

VO(LOWV)

Pre-

Conditioning

Phase

Thermal

Regulation

Phase

Current

Regulation

Phase

Voltage Regulation and

Charge Termination

Phase

Battery

Voltage,

V(OUT)

Battery Current,

I(OUT)

Charge

Complete

Status,

Charger

Off

IO(PRECHG)

T(THREG)

Temperature, Tj

DONE

I(TERM)

T(PRECHG)

T(CHG)

Figure 8. Charging Profile With Thermal Regulation

DONE

8.3 Feature Description

8.3.1 Power-Down or Undervoltage Lockout (UVLO)

The bq2404x family is in power down mode if the IN terminal voltage is less than UVLO. The part is considered

âdeadâ and all the terminals are high impedance. Once the IN voltage rises above the UVLO threshold the IC will

enter Sleep Mode or Active mode depending on the OUT terminal (battery) voltage.

8.3.2 Power-up

The IC is alive after the IN voltage ramps above UVLO (see sleep mode), resets all logic and timers, and starts

to perform many of the continuous monitoring routines. Typically the input voltage quickly rises through the

UVLO and sleep states where the IC declares power good, starts the qualification charge at 100mA, sets the

input current limit threshold base on the ISET2 terminal, starts the safety timer and enables the CHG terminal.

See Figure 9.

8.3.3 Sleep Mode

If the IN terminal voltage is between than VOUT+VDT and UVLO, the charge current is disabled, the safety timer

counting stops (not reset) and the PG and CHG terminals are high impedance. As the input voltage rises and the

charger exits sleep mode, the PG terminal goes low, the safety timer continues to count, charge is enabled and

the CHG terminal returns to its previous state. See Figure 10.

8.3.4 New Charge Cycle

A new charge cycle is started when a good power source is applied, performing a chip disable/enable (TS

terminal/BAT_EN), exiting Termination and Timer Disable Mode (TTDM), detecting a battery insertion or the OUT

voltage dropterminalg below the VRCH threshold. The CHG terminal is active low only during the first charge

cycle, therefore exiting TTDM or a dropterminalg below VRCH will not turn on the CHG terminal FET, if the CHG

terminal is already high impedance.

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Product Folder Links: bq24040 bq24041 bq24045

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