BQ2014H_15 Datasheet, PDF (16/28 Pages) Texas Instruments – Low-Cost NiCd/NiMH Gas Gauge IC

bq2014H
RCAC varies from 0 to 64h representing relative state-
of-charge from 0 to 100%.
Current Scale Register (VSRH/VSRL)
The VSRH register (address = 12h) and the VSRL regis-
ter (address = 13h) report the average signal across the
SR and V_SS pins. The bq2050H updates this register
pair every 22.5s. V_SRH (high-byte) and V_SRL (low-byte)
form a 16-bit signed integer value representing the aver-
age current during this time. The battery pack current
can be calculated from:
|I(mA)| = (V_SRH ∗ 256 + V_SRL)/(8 ∗R_S)
where:
R_S = sense resistor value in Ω.
V_SRH = high-byte value of battery current
V_SRL = low-byte value of battery current
The bq2014H indicates an average discharge current
with a “1” in the MSB position of the VSRH register. To
calculate discharge current, use the 2’s complement if
the concatenated register contents in the above equa-
tion.
Discharge Count Register (DCR)
The DCR register (address = 18h) stores the high-byte of
the discharge count. DCR is reset to zero at the start of
a valid discharge cycle and can count to a maximum of
FFh. DCR will not increment if EDV1 = 1 and will not
roll over from FFh.
Program Pin Full Count (PPFC)
The PPFC register contains information concerning the
program pin configuration. This information is used to
determine the data integrity of the bq2014H. The only
approved user application for this register is to
write a zero to this register as part of a reset re-
quest.
The recommended reset method for the bq2014H is
I Write PPFC to zero
I Write LMD to zero
After these operations, a software reset will occur.
Resetting the bq2014H sets the following:
I LMD = PFC
I CPI, VDQ, RCAC, NACH/L, CACH/L, SAEH/L,
NMCV = 0
I CI and BRP = 1
Voltage Offset (V_OS) Interrupt (INTSS)
The INTSS register (address = 38h) is useful during in-
tial characterization of bq2014H designs. When the
bq2014H counts a charge pulse, CHGI (bit 0) will be set
to 1. When the bq2014H counts a discharge pulse,
DCHGI (bit 3) will be set to 1. All other locations in the
INTSS register are reserved.
Display
The bq2014H can directly display capacity information
using low-power LEDs. If LEDs are used, the program
pins should be resistively tied to V_CC or V_SS for a pro-
gram high or program low, respectively.
The bq2014H displays the battery charge state in relative
mode. In relative mode, the battery charge is represented
as a percentage of the LMD. Each LED segment repre-
sents 20% of the LMD.
The capacity display is also adjusted for the present bat-
tery temperature and discharge rate. The temperature
adjustment reflects the available capacity at a given
temperature but does not affect the NAC register. The
temperature adjustments are detailed in the CACT and
CACD register descriptions.
When DISP is tied to V_CC, the SEG_1–5 outputs are inac-
tive. When DISP is left floating, the display becomes ac-
tive whenever the bq2014H detects a charge in progress
V_SRO > V_SRQ. When pulled low, the segment outputs be-
come active for a period of four seconds, ± 0.5 seconds.
The segment outputs are modulated as two banks, with
segments 1, 3, and 5 alternating with segments 2 and 4.
The segment outputs are modulated at approximately
100Hz with each segment bank active for 30% of the pe-
riod.
SEG₁ blinks at a 4Hz rate whenever V_SB has been de-
tected to be below V_EDV1 (EDV1 = 1), indicating a low-
battery condition. V_SB below V_EDVF (EDVF = 1) disables
the display output.
Microregulator
A micropower source for the bq2014H can be inexpen-
sively built using a FET and an external resistor. (See
Figure 1.)
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