ADC12040 Datasheet, PDF (16/29 Pages) National Semiconductor (TI) – 12-Bit, 40 MSPS, 340 mW A/D Converter with Internal Sample-and-Hold

ADC12040
SNAS135G – FEBRUARY 2001 – REVISED MARCH 2013
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Single-Ended Operation
Single-ended performance is lower than with differential input signals. For this reason, single-ended operation is
not recommended. However, if single-ended operation is required, and the resulting performance degradation is
acceptable, one of the analog inputs should be connected to the d.c. common mode voltage of the driven input.
The peak-to-peak differential input signal should be twice the reference voltage to maximize SNR and SINAD
performance (Figure 19(b)). For example, set V_REF to 1.0V and bias V_IN− to 1.0V and drive V_IN+ with a signal
range of 0V to 2.0V.
Because very large input signal swings can degrade distortion performance, better performance with a single-
ended input can be obtained by reducing the reference voltage while maintaining a full-range output. and indicate
the input to output relationship of the ADC12040.
Driving the Analog Inputs
The V_IN+ and the V_IN− inputs of the ADC12040 consist of an analog switch followed by a switched-capacitor
amplifier. The capacitance seen at the analog input pins changes with the clock level, appearing as 8 pF when
the clock is low, and 7 pF when the clock is high. Although this difference is small, a dynamic capacitance is
more difficult to drive than is a fixed capacitance, so choose the driving amplifier carefully. The LMH6550, the
LMH6702 and the LMH6628 are a good amplifiers for driving the ADC12040.
The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving
source tries to compensate for this, it adds noise to the signal. To prevent this, use an RC at each of the inputs,
as shown in Figure 22 and Figure 23. These components should be placed close to the ADC because the input
pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter the input. The
capacitors are for Nyquist applications and should be eliminated for undersampling applications.
The LMH6550 and the LMH6552 are excellent devices for driving the ADC12040, especially when single-ended
to differential conversion with d.c. coupling is necessary. An example of the use of the LMH6550 to drive the
analog input of the ADC12040 is shown in Figure 22.
For high frequency, narrow band applications, a transformer is generally the recommended way to drive the
analog inputs, as shown in Figure 23.
Input Common Mode Voltage
The input common mode voltage, V_CM, should be in the range indicated in OPERATING CONDITIONS and be of
a value such that the peak excursions of the analog input signal do not go more negative than ground or more
positive than the V_A supply voltage. The nominal V_CM should generally be equal to V_REF/2, but V_RM can be used
as a V_CM source as long as V_RM need not supply more than 10 µA of current. Figure 22 shows the use of the V_RM
output to drive the V_CM input of the LMH6550. The common mode output voltage of the LMH6550 is equal to the
V_CM input input voltage.
DIGITAL INPUTS
The digital TTL/CMOS compatible inputs consist of CLK, OE and PD.
The CLK Input
The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock
signal in the range of 100 kHz to 50 MHz with rise and fall times of less than 3ns. The trace carrying the clock
signal should be as short as possible and should not cross any other signal line, analog or digital, not even at
90°.
If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point
where the accuracy of the output data will degrade. This is what limits the lowest sample rate to 100 ksps.
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC12040 is designed to maintain performance over a range of duty cycles. While it is
specified and performance is ensured with a 50% clock duty cycle, performance is typically maintained over a
clock duty cycle range of 45% to 55%.
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