OMAP-L132_14 Datasheet, PDF (158/232 Pages) Texas Instruments – DSP+ ARM Processor

OMAP-L132
SPRS762D – AUGUST 2011 – REVISED MARCH 2014
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Table 6-65. Additional SPI0 Master Timings, 4-Pin Enable Option ^(1)(2)(3)
NO.
PARAMETER
1.2V
MIN
MAX
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P+5
17 t_{d(ENA_SPC)M}
Delay from slave assertion of SPI0_ENA
active to first SPI0_CLK from master.⁽⁴⁾
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
0.5M+3P+5
3P+5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5M+3P+5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P+5
18 t_{d(SPC_ENA)M}
Max delay for slave to deassert SPI0_ENA
after final SPI0_CLK edge to ensure
master does not begin the next transfer.⁽⁵⁾
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
P+5
0.5M+P+5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+5
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-63).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
1.1V
MIN
MAX
3P+5
0.5M+3P+5
3P+5
0.5M+3P+5
0.5M+P+5
P+5
0.5M+P+5
P+5
Table 6-66. Additional SPI0 Master Timings, 4-Pin Chip Select Option ^(1)(2)(3)
NO.
PARAMETER
19 t_{d(SCS_SPC)M}
Delay from SPI0_SCS active to first
SPI0_CLK^{(4) (5)}
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
1.2V
MIN
2P-1
MAX
0.5M+2P-1
2P-1
0.5M+2P-1
1.1V
MIN
2P-2
MAX
0.5M+2P-2
2P-2
0.5M+2P-2
1.0V
MIN
MAX
3P+6
0.5M+3P+6
3P+6
0.5M+3P+6
0.5M+P+6
P+6
0.5M+P+6
P+6
UNIT
ns
ns
1.0V
MIN
2P-3
MAX
UNIT
0.5M+2P-3
ns
2P-3
0.5M+2P-3
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-63).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
158 Peripheral Information and Electrical Specifications
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