OMAP-L132_14 Datasheet, PDF (132/232 Pages) Texas Instruments – DSP+ ARM Processor

OMAP-L132
SPRS762D – AUGUST 2011 – REVISED MARCH 2014
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6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
6.13.1 MMCSD Peripheral Description
The device includes an two MMCSD controllers which are compliant with MMC V4.0, Secure Digital Part 1
Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.
The MMC/SD Controller have following features:
• MultiMediaCard (MMC)
• Secure Digital (SD) Memory Card
• MMC/SD protocol support
• SD high capacity support
• SDIO protocol support
• Programmable clock frequency
• 512 bit Read/Write FIFO to lower system overhead
• Slave EDMA transfer capability
The device MMC/SD Controller does not support SPI mode.
6.13.2 MMCSD Peripheral Register Description(s)
Table 6-41. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers
MMCSD0
BYTE ADDRESS
0x01C4 0000
0x01C4 0004
0x01C4 0008
0x01C4 000C
0x01C4 0010
0x01C4 0014
0x01C4 0018
0x01C4 001C
0x01C4 0020
0x01C4 0024
0x01C4 0028
0x01C4 002C
0x01C4 0030
0x01C4 0034
0x01C4 0038
0x01C4 003C
0x01C4 0040
0x01C4 0044
0x01C4 0048
0x01C4 0050
0x01C4 0064
0x01C4 0068
0x01C4 006C
0x01C4 0070
0x01C4 0074
MMCSD1
BYTE ADDRESS
0x01E1 B000
0x01E1 B004
0x01E1 B008
0x01E1 B00C
0x01E1 B010
0x01E1 B014
0x01E1 B018
0x01E1 B01C
0x01E1 B020
0x01E1 B024
0x01E1 B028
0x01E1 B02C
0x01E1 B030
0x01E1 B034
0x01E1 B038
0x01E1 B03C
0x01E1 B040
0x01E1 B044
0x01E1 B048
0x01E1 B050
0x01E1 B064
0x01E1 B068
0x01E1 B06C
0x01E1 B070
0x01E1 B074
ACRONYM
MMCCTL
MMCCLK
MMCST0
MMCST1
MMCIM
MMCTOR
MMCTOD
MMCBLEN
MMCNBLK
MMCNBLC
MMCDRR
MMCDXR
MMCCMD
MMCARGHL
MMCRSP01
MMCRSP23
MMCRSP45
MMCRSP67
MMCDRSP
MMCCIDX
SDIOCTL
SDIOST0
SDIOIEN
SDIOIST
MMCFIFOCTL
REGISTER DESCSRIPTION
MMC Control Register
MMC Memory Clock Control Register
MMC Status Register 0
MMC Status Register 1
MMC Interrupt Mask Register
MMC Response Time-Out Register
MMC Data Read Time-Out Register
MMC Block Length Register
MMC Number of Blocks Register
MMC Number of Blocks Counter Register
MMC Data Receive Register
MMC Data Transmit Register
MMC Command Register
MMC Argument Register
MMC Response Register 0 and 1
MMC Response Register 2 and 3
MMC Response Register 4 and 5
MMC Response Register 6 and 7
MMC Data Response Register
MMC Command Index Register
SDIO Control Register
SDIO Status Register 0
SDIO Interrupt Enable Register
SDIO Interrupt Status Register
MMC FIFO Control Register
132 Peripheral Information and Electrical Specifications
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