VECANA01_13 Datasheet, PDF (15/17 Pages) Texas Instruments – 10-Channel, 12-Bit DATA ACQUISITION SYSTEM

R_A
+5V
+U_B
IN
OUT
+
5.6V
C_A
R_D
–U_B
IN
OUT
+
5.6V
C_{A RD}
–5V
R_A
Voltage Regulator,
Current Limited
FIGURE 7. Power Supply of VECANA01.
C_R
C_R
+
+
C_D
C_B
C_A
C_B
+
+
C_D
C_B
C_A
C_B
Ground Plane
VECANA01
REFIN
REFOUT
UP5V
UDP5V
AGND
DGND
REFGND
UDN5V
UN5V
CONNECTION BETWEEN VECANA01 AND DSP
The interface between the VECANA01 and dSMC101 com-
prises the control signals for the A/D converters (ADCLK,
ADCONV, ADIN, ADOUT1-3, NPSH, ADBUSY and
DATACLK) and the comparator signals (X_COMP and
X_ILIM). The signal levels and the driver capacity of the
two chips are compatible. In order to avoid noise injection of
the digital power supply into the analog VECANA01 chip,
it is recommended to damp all digital lines with an interme-
diate resistor of approximately 100Ω as near as possible to
the analog chip.
VECANA01
100Ω
Motor
Control
DSP
SICAN dSMC101 INTERFACE
The internal logic of the VECANA01 is designed for easy
control and data interface with DSPs. Figure 9 shows the
interface for loading the input control word from the DSP
data bus into the serial input of the VECANA01.
Phase-
Currents
IUP/N
IVP/N
IWP/N
A1P/N
Encoder1
B1P/N
A2P/N
Encoder2
B2P/N
AN1P/N
Auxillary
Inputs ^AN2P/N
AN3P/N
VECANA01
U/V/W_COMP
U/V/W_ILIM
A_1, B_1
A_2, B_2
ADCLK
ADCONV
ADOUT1-3
ADIN
NPSH
Sican
dSMC101
FIGURE 8. Damping of All Digital Lines.
FIGURE 9. DSP Interface for Sican dSMC101.
VECANA01
15
SBAS155