VECANA01_13 Datasheet, PDF (11/17 Pages) Texas Instruments – 10-Channel, 12-Bit DATA ACQUISITION SYSTEM

INPUT/OUTPUT
The VECANA01 is designed for bipolar input voltages and
uses a binary two’s complement digital output code. A
programmable gain function is associated with each A/D
converter. This changes the full-scale analog input range and
the analog resolution of the converter. Details are shown in
Table IX.
DIFFERENTIAL AND COMMON-MODE INPUT
VOLTAGES
The VECANA01 is designed with full differential signal
paths all the way from the multiplexer inputs through to the
input of the A/D converters. This was done to provide
superior high frequency noise rejection. As is common with
most differential input semiconductor devices, there are
compound restrictions on the combination of differential
and common-mode input voltages. This matter is made
slightly more complicated by the fact that most of the analog
inputs are capable of being affected by the programmable
gain function. The possible differential and single-ended
configurations are shown in Figures 4a and 4b. The maxi-
mum differential and common-mode restrictions are shown
in Table III.
GAIN SELECT CODE
0
1
2
3
Gain
Full Scale Range
(V_D with V_CM = 0)
Largest Positive
Common Mode
Voltage, V_CM+
Largest Negative
Common Mode
Voltage, V_CM–
5.0V/V
±0.5V
2.5V/V
±1.0V
1.25V/V
±2.0V
1.0V/V
±2.5V
+2.7V
+2.4V
+1.9V
+1.6V
–2.7V
–2.4V
–1.9V
–1.6V
TABLE III. Differential and Common Mode Voltage
Restrictions.
(A)
+
V_D
2
–
+
V_D
2
–
V_CM
+
–
(B)
+
V_D
–
+
V_CM
–
IUP
IUP
V_D
2
IUN
V_D
IUN
2
IU
IUP
V_D
IUN
V_CM
V_CM
V_CM
FIGURE 4. (a) Differential Signal Source. (b) Single-ended
Input.
VECANA01
SBAS155
INPUT SETUP
As the A/D converters are converting and transmitting their
serial digital data for one conversion cycle, a setup word is
received to be used for the next conversion cycle. The 13-bit
word is supplied at the ADIN pin (see Figure 1), and is
stored in the buffered Input Setup Register. The Input Select
and Gain Select portions of the word are decoded and
determine the state of the multiplexers and PGAs (see
CONFIGURABLE PARAMETERS section).
INPUT MULTIPLEXER AND SAMPLE HOLD
SELECTION
The Input Select portion of the ADIN word (bits 10, 11 and
12) (see Figure 2) are decoded and determine the open/
closed condition of the multiplexer switches. This in turn
determines which input signals are connected to the sample
and holds and which sample and holds are connected to the
PGAs/ADCs.
SIGN OF THE INPUT SIGNALS
The VECANA01 contains seven comparators, which ac-
quire the signals of the first seven input analog signals. The
digital outputs of the sign comparators are the signals
X_COMP. If the positive input value is greater than the
negative input value, the X-COMP output becomes High
(logic “1”) or if the reverse, the X-COMP output is Low
(logic “0”), (see Table IV).
IUP – IUN
A1P – A1N
A2P – A2P
IVP – IVN
B1P – B1N
B2P – B2N
IWP – IWN
>0
<0
TABLE IV. Input - Output Relation.
U_COMP
A_1
A_2
V_COMP
B_1
B_2
W_COMP
1
0
The typical hysteresis value of comparators U_COMP,
V_COMP and W_COMP is 10mV. The typical hysteresis
value of comparators A_1, A_2, B_1, and B_2 is 50mV. AC
motor control applications will typically use 10mV hysteresis
for phase current measurement and 50mV hysteresis for
positioning sensor measurement.
OVER RANGE RECOGNITION
The VECANA01 also includes three window comparators for
the three input signals IU, IV and IW. Each window compara-
tor is composed of two comparators that are monitoring the
input value on the positive range limit (U_PLIM) and negative
range limit (U_NLIM). The output values of the window com-
parators are output via the pins U_ILIM, V_ILIM and
W_ILIM. The two range limiting values are symmetrical to
the zero point (U_NLIM = –U_PLIM) and are determined by pin
11