TPD3S014_15 Datasheet, PDF (15/30 Pages) Texas Instruments – TPD3S0x4 Current Limit Switch and D+/D– ESD Protection for USB Host Ports

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TPD3S014, TPD3S044
SLVSCP4B – OCTOBER 2014 – REVISED AUGUST 2015
Feature Description (continued)
Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred
and the TPD3S0x4s have abruptly reduced OUT current. Energy stored in the inductance will drive the OUT
voltage down and potentially negative as it discharges. Applications with large output inductance (such as from a
cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing
USB standard applications, a 120 µF minimum output capacitance is required. Typically a 150-µF electrolytic
capacitor is used, which is sufficient to control voltage undershoots. However, if the application does not require
120 µF of capacitance, and there is potential to drive the output negative, a minimum of 10-µF ceramic
capacitance on the output is recommended. The voltage undershoot should be controlled to less than 1.5 V for
10 µs.
8.4 Device Functional Modes
8.4.1 Operation With V_IN < 4 V (Minimum V_IN)
These devices operate with input voltages above 4 V. The maximum UVLO voltage on IN is 4 V and the devices
will operate at input voltages above 4 V. Any voltage below 4 V may not work with these devices. The minimum
UVLO is 3.5 V, so some devices may work between 3.5 V and 4 V. At input voltages below the actual UVLO
voltage, these devices will not operate.
8.4.2 Operation With EN Control
The enable rising edge threshold voltage is 1.45 V typical and 2 V maximum. With EN held below that voltage
the device is disabled and the load switch will be open. The IC quiescent current is reduced in this state. When
the EN pin is above its rising edge threshold and the input voltage on the IN pin is above its UVLO threshold, the
device becomes active. The load switch is closed, and the current limit feature is enabled. The output voltage on
OUT will ramp up with the soft start value T_ON in order to prevent large inrush current surges on V_BUS due to a
heavy capacitive load. When EN voltage is lowered below is falling edge threshold, the device output voltage will
also ramp down with soft turn off value T_OFF to prevent large inductive voltages being presented to the system in
the case a large load current is following through the device.
8.4.3 Operation of Level 4 IEC61000-4-2 ESD Protection
Regardless of which functional mode the devices are in, TPD3S0x4 will provide Level 4 IEC61000-4-2 ESD
Protection on the pins of the USB connector.
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