TPD3S014_15 Datasheet, PDF (14/30 Pages) Texas Instruments – TPD3S0x4 Current Limit Switch and D+/D– ESD Protection for USB Host Ports

TPD3S014, TPD3S044
SLVSCP4B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
Feature Description (continued)
The TPD3S0x4s thermal cycle if an overload condition is present long enough to activate thermal limiting in any
of the above cases. This is due to the relatively large power dissipation [(V_IN – V_OUT) × I_OS] driving the junction
temperature up. The devices turn off when the junction temperature exceeds 135°C (min) while in current limit.
The devices remains off until the junction temperature cools 20°C and then restarts.
There are two kinds of current limit profiles typically available in TI switch products similar to the TPD3S0x4s.
Many older designs have an output I vs V characteristic similar to the plot labeled "Current Limit with Peaking" in
Figure 29. This type of limiting can be characterized by two parameters, the current limit corner (I_OC), and the
short circuit current (I_OS). I_OC is often specified as a maximum value. The TPD3S0x4 parts do not present
noticeable peaking in the current limit, corresponding to the characteristic labeled "Flat Current Limit" in
Figure 29. This is why the I_OC parameter is not present in the Electrical Characteristics tables.
Current Limit
with Peaking
Flat Current
Limit
V _IN
Slope = -R_DS(ON)
Decreasing
Load
Resistance
V _IN
Slope = -R_DS(ON)
Decreasing
Load
Resistance
0V
0A
I_OUT
I_OS I_OC
0V
0A
I_OUT
I_OS
Figure 29. Current Limit Profiles
8.3.5 Output Discharge
A 470-Ω (typical) output discharge resistance will dissipate stored charge and leakage current on OUT when the
TPD3S0x4s are in UVLO or disabled. The pull-down circuit will lose bias gradually as V_IN decreases, causing a
rise in the discharge resistance as V_IN falls towards 0 V.
8.3.6 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance should be
optimized for the particular application. For all applications, a 0.1 µF or greater ceramic bypass capacitor
between IN and GND is recommended as close to the device as possible for local noise decoupling.
All protection circuits such as the TPD3S0x4s will have the potential for input voltage overshoots and output
voltage undershoots.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input
voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high
impedance (before turn on). Theoretically, the peak voltage is 2 times the applied. The second cause is due to
the abrupt reduction of output short circuit current when the TPD3S0x4s turn off and energy stored in the input
inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the
TPD3S0x4s outputs are shorted. Applications with large input inductance (for example, connecting the evaluation
board to the bench power-supply through long cables) may require large input capacitance reduce the voltage
overshoot from exceeding the absolute maximum voltage of the device. The fast current-limit speed of the
TPD3S0x4s to hard output short circuits isolates the input bus from faults. However, ceramic input capacitance in
the range of 1 to 22 µF adjacent to the TPD3S0x4s inputs aids in both speeding the response time and limiting
the transient seen on the input power bus. Momentary input transients to 6.5 V are permitted.
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