TPA3244 Datasheet, PDF (15/32 Pages) Texas Instruments – 100W peak PurePath Ultra-HD Pad Down Class-D Amplifier

www.ti.com
TPA3244
SLASEC6 – APRIL 2016
8.2.3 Typical Application, Single Ended (1N) SE
The TPA3244 device can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in
2.1 mixed 1x BTL + 2x SE mode depending on output power conditions and system design.
+12V
INPUT_A
INPUT_B
INPUT_C
INPUT_D
/RESET
/FAULT
/CLIP_OTW
3R3
470uF 100nF
10µF
10µF
10µF
10µF
100nF
22k
30k
1µF
1µF
470nF
100nF
3R3
100nF
1
GVDD_AB
2
VDD
3 _M1
4 _M2
5
INPUT_A
6 _{INPUT_B}
7
OC_ADJ
8 _{FREQ_ADJ}
9
OSC_IOM
10 _{OSC_IOP}
11 _DVDD
12 _GND
TPA3250
13 _GND
14
AVDD
15 _{C_START}
16 _{INPUT_C}
17 _{INPUT_D}
18 _/RESET
19
/FAULT
20 _VBG
21
/CLIP_OTW
22
GVDD_CD
44
BST_A
43
BST_B
42
GND
GND ⁴¹
OUT_A ⁴⁰
OUT_A ³⁹
38
PVDD_AB
37
PVDD_AB
36
PVDD_AB
35
OUT_B
34
GND
GND ³³
OUT_C ³²
31
PVDD_CD
30
PVDD_CD
29
PVDD_CD
28
OUT_D
27
OUT_D
GND ²⁶
25
GND
24
BST_C
23
BST_D
33nF
33nF
1µF
470uF
1µF
1µF
1µF 470uF
33nF
33nF
15µH
15µH
15µH
15µH
470uF
10nF
1nF
1µF
3R3
1µF
1nF
3R3
10nF
470uF
PVDD
GND
470uF
10nF
1nF
1µF
3R3
1µF
1nF
3R3
10nF
470uF
Figure 7. Typical Single Ended (1N) SE Application
8.2.3.1 Design Requirements
Refer to Stereo BTL Application for the Design Requirements.
Table 9. Design Requirements, SE Application
DESIGN PARAMETER
Low Power (Pull-up) Supply
Mid Power Supply 1 2V
High Power Supply
Mode Selection
Analog Inputs
Output Filters
Speaker Impedance
EXAMPLE
3.3 V
12 V
12 - 32 V
M2 = H
M1 = H
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ±3.9 V (peak, max)
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Inductor-Capacitor Low Pass FIlter (15 µH + 680 nF)
2-8Ω
8.2.3.2 Detailed Design Procedures
Refer to Stereo BTL Application for the Detailed Design Procedures.
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPA3244
Submit Documentation Feedback
15