TLC59283 Datasheet, PDF (15/25 Pages) Texas Instruments – 16-Channel, Constant-Current LED Driver with Pre-Charge FET

TLC59283
www.ti.com
SBVS199A – JUNE 2012 – REVISED JUNE 2012
REGISTER CONFIGURATION
The TLC59283 has a 16-bit shift register and an output on or off data latch. Both the shift register and data latch
are 16 bits long and are used to turn the constant-current outputs on and off. Figure 21 shows the shift register
and data latch configuration. The data at the SIN pin are shifted into the 16-bit shift register LSB at the rising
edge of the SCLK pin; SOUT data change at the SCLK rising edge.
16-Bit Shift Register (1 Bit ´ 16 Channels)
SOUT
MSB
15
14
13
12
11
On or Off
On or Off
On or Off
On or Off
Data for
Data for
Data for
Data for
¼
OUT15
OUT14
OUT13
OUT12
LSB
4
3
2
1
0
On or Off
Data for
OUT3
On or Off
Data for
OUT2
On or Off
Data for
OUT1
On or Off
Data for
OUT0
SIN
SCLK
¼
MSB
15
14
13
12
11
On or Off
On or Off
On or Off
On or Off
Data for
Data for
Data for
Data for
¼
OUT15
OUT14
OUT13
OUT12
LSB
4
3
2
1
0
On or Off
Data for
OUT3
On or Off
Data for
OUT2
On or Off
Data for
OUT1
On or Off
Data for
OUT0
LAT
Output On or Off Data Latch (1 Bit ´ 16 Channels)
16 Bits
To Constant-Current Driver Control Block
Figure 21. 16-Bit Shift Register and Output On or Off Data Latch Configuration
The output on or off data in the 16-bit shift register continue to transfer to the output on or off data latch while
LAT is high. Therefore, if the data in the 16-bit shift register are changed when LAT is high, the data in the data
latch are also changed. The data in the data latch are held when LAT is low. When the device initially powers on,
the data in the output on or off shift register and latch are not set to default values; on or off control data must be
written to the on or off control data latch before turning the constant-current output on. All constant-current
outputs are forced off when BLANK is high. The OUTn on or off outputs are controlled by the data in the output
on or off data latch. The writing data truth table and timing diagram are shown in Table 3 and Figure 22,
respectively.
SCLK
↑
↑
↑
↓
↓
Table 3. Truth Table in Operation
LAT
High
Low
High
—
—
BLANK
Low
Low
Low
Low
High
SIN
Dn
Dn + 1
Dn + 2
Dn + 3
Dn + 3
OUT0…OUT7…OUT15
Dn…Dn – 7…Dn – 15
No change
Dn + 2…Dn – 5…Dn – 13
Dn + 2…Dn – 5…Dn – 13
Off
SOUT
Dn – 15
Dn – 14
Dn – 13
Dn – 13
Dn – 13
Copyright © 2012, Texas Instruments Incorporated
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