THS4302_14 Datasheet, PDF (15/28 Pages) Texas Instruments – WIDEBAND FIXED-GAIN AMPLIFIER

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when they are not properly terminated to the
ground plane over the area and along the
perimeter of the power plane by high frequency
capacitors. Doing so ensures that there are no
power plane resonances in the needed frequency
range. Values used are in the range of 2 pF - 50
pF, depending on the frequencies to be
suppressed, with numerous vias for each. Using
0402 or smaller component sizes is
recommended. An approximate expression for
the resonant frequencies associated with a length
of one of the power plane dimensions is given in
the following equation. Note that a power plane of
arbitrary shape can have a number of resonant
frequencies. A power plane without distributed
capacitors and with active parts near the center
of the plane usually has n even (≥ 2) due to the
half wave resonant nature of the plane.
n (44 GHz mm)
frequency_res [
ȏ
where:
frequency_res = the approximate power plane resonant
frequencies in GHz
ȏ^{= the length of the power plane dimensions in}
millimeters
n = an integer (n > 1) related to the mode of the oscillation
For guidance on capacitor spacing over the area
of the ground plane, specify the lowest resonant
frequency to be tolerated, then solve using the
equation above, with n = 2. Use this length for
the capacitor spacing. It is recommended that a
power plane, if used, be either small enough, or
decoupled as described, so that there are no
resonances in the frequency range of interest. An
alternative is to use a ferrite bead outside the
op-amp, high-frequency bypass capacitors to
decouple the amplifier, and mid- and
high-frequency bypass capacitors, from the
power plane. When a trace is used to deliver
power, its approximate self-resonance is given by
the equation above, substituting the trace length
for power plane dimension.
4. Bypass capacitors, because they have a
self-inductance, resonate with each other. To
achieve optimum transfer characteristics through
2 GHz, it is recommended that the bypass
arrangement employed in the prototype board be
used. The 30.1-Ω resistor in series with the
0.1-μF capacitor reduces the Q of the resonance
of the lumped parallel elements including the
0.1-μF and 47-pF capacitors, and the power
supply input of the amplifier. The ferrite bead
isolates the low-frequency 22-μF capacitor and
power plane from the remainder of the bypass
network.
5. By removing the 30.1-Ω resistor and ferrite bead,
the frequency response characteristic above 400
MHz may be modified. However, bandwidth,
distortion, and transient response remain optimal.
THS4302
SLOS403H – OCTOBER 2002 – REVISED AUGUST 2006
6. Recommended values for power supply
decoupling include a bulk decoupling capacitor
(22 μF), a ferrite bead with a high self-resonant
frequency, a mid-range decoupling capacitor (0.1
μF) in series with a 30.1-Ω resistor, and a
high-frequency decoupling capacitor (47 pF).
BOARD LAYOUT
Printed-Circuit Board Layout Techniques for
Optimal Performance
Achieving optimum performance with a high
frequency amplifier like the THS4302 requires careful
attention to board layout parasitics and external
component types.
Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. However,
if using a transmission line at the I/O, then place
the matching resistor as close to the part as
possible. Except for when transmission lines are
used, parasitic capacitance on the output and the
noninverting input pins can react with the load
and source impedances to cause unintentional
band limiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be
opened in all of the ground and power planes
around those pins. Otherwise, ground planes and
power planes (if used) should be unbroken
elsewhere on the board, and terminated as
described in the Power Supply Decoupling
section.
2. Minimize the distance (< 0.25”) from the
power supply pins to high frequency 0.1-μF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. Note that each millimeter of a line,
that is narrow relative to its length, has ~ 0.8 nH
of inductance. The power supply connections
should always be decoupled with the
recommended capacitors. If not properly
decoupled, distortion performance is degraded.
Larger (6.8-μF to 22-μF) decoupling capacitors,
effective at lower frequency, should also be used
on the main supply lines, preferably decoupled
from the amplifier and mid- and high-frequency
capacitors by a ferrite bead. See the Power
Supply Decoupling Techniques section. The
larger caps may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PC board. A very
low inductance path should be used to connect
the inverting pin of the amplifier to ground. A
minimum of 5 vias as close to the part as
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