THS4302_14 Datasheet, PDF (14/28 Pages) Texas Instruments – WIDEBAND FIXED-GAIN AMPLIFIER

THS4302
SLOS403H – OCTOBER 2002 – REVISED AUGUST 2006
V_S+
+
22 µF ^FB
47 pF
50-Ω Source
R_g
*2.5 V
V_I
49.9 Ω
R_f
_
+ _THS4302
0.1 µF
30.1 Ω
*2.5 V
FB = Ferrite Bead
* = Low Impedance
R_ISO ^{0.1 µF}
16.5 Ω
68 pf
1.82 kΩ
IN
ADS807
12-Bit,
CM 53 Msps
IN
0.1 µF
For best performance, high-speed ADCs
should be driven differentially. See the
THS4500 family of devices for more
information.
Figure 47. Driving an ADC With a Single-Ended
Input
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The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4302. Long PC board traces,
unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4302 output pin (see Board Layout
Guidelines).
The criterion for setting this R_(ISO) resistor is a
maximum bandwidth, flat frequency response at the
load.
1
0.5
R_(ISO) = 24.9 Ω,
C_L = 10 pF
0
-0.5
-1
R_(ISO) = 8 Ω,
C_L = 100 pF
-1.5
-2
R_(ISO) = 12.1 Ω,
C_L = 47 pF
-2.5
V_S = 5 V
-3
10 M
100 M
1G
f - Frequency - Hz
Figure 48. Driving Capacitive Loads
Driving Capacitive Loads
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
High-speed amplifiers like the THS4302 can be
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed
directly on the output pin. When the amplifier's
open-loop output resistance is considered, this
capacitive load introduces an additional pole in the
signal path that can decrease the phase margin.
When the primary considerations are frequency
response flatness, pulse response fidelity, or
distortion, the simplest and most effective solution is
to isolate the capacitive load from the feedback loop
by
inserting a series isolation resistor between the
amplifier output and the capacitive load.
Power Supply Decoupling Techniques and
Recommendations
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of
performance.
1. Place decoupling capacitors as close to the
power supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply. Inductance in series
with the bypass capacitors will degrade
performance. Note that a narrow lead or trace
has about 0.8 nH of inductance for every
millimeter of length. Each printed-circuit board
(PCB) via also has between 0.3 and 0.8 nH
depending on length and diameter. For these
reasons, it is recommended to use a power
supply trace about the width of the package for
each power supply lead to the capacitors, and 3
or more vias to connect the capacitors to the
ground plane.
2. Placement priority should put the smallest valued
capacitors closest to the device.
3. Solid power planes can lead to PCB resonances
14
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