THS1209_14 Datasheet, PDF (15/34 Pages) Texas Instruments – 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

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THS1209
SLAS288B – JULY 2000 – REVISED DECEMBER 2002
CONVERSION MODE
During conversion, the ADC operates with a free running external clock signal applied to the input CONV_CLK. With
every falling edge of the CONV_CLK signal a new converted value is available to the databus with the corresponding
read signal. The THS1209 offers up to two analog inputs to be selected. It is important to provide the channel
information to the system, this means to know which channel is available to the databus. The signal SYNC is disabled
for the selection of one analog input since this information is not required for one analog input.
Figure 25 shows the timing of the conversion when one analog input channel is selected. The maximum throughput
rate is 8 MSPS in this mode. There is a certain timing relationship required for the read signal with respect to the
conversion clock. This can be seen in Figure 26 and Table 2. A more detailed description of the timing is given in the
section timing and signal description of the THS1209.
Sample N
Channel 1
Sample N+1
Channel 1
Sample N+2
Channel 1
Sample N+3
Channel 1
Sample N+4
Channel 1
Sample N+5
Channel 1
Sample N+6
Channel 1
AIN
CONV_CLK
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
READ^†
Data N–4
Channel 1
Data N–3
Channel 1
Data N–2
Channel 1
Data N–1
Channel 1
Data N
Channel 1
Data N+1
Channel 1
†_{READ is the logical combination from CS0, CS1 and RD}
Figure 25. Conversion Timing in 1-Channel Operation
Data N+2
Channel 1
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