THS1209_14 Datasheet, PDF (14/34 Pages) Texas Instruments – 12-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS1209
SLAS288B – JULY 2000 – REVISED DECEMBER 2002
DETAILED DESCRIPTION
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Reference Voltage
The THS1209 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V
and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and
REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the
upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
Analog Inputs
The THS1209 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.
Converter
The THS1209 uses a 12-bit pipelined multistaged architecture which achieves a high sample rate with low power
consumption. The THS1209 distributes the conversion over several smaller ADC sub-blocks, refining the conversion
with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion
requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier
(SHA) within each of the stages permits the first stage to operate on a new input sample while the second through
the eighth stages operate on the seven preceding samples.
Conversion
An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new conversion
is started with every falling edge of the applied clock signal. The conversion values are available at the output with
a latency of 5 clock cycles.
SYNC
In multichannel mode, the first SYNC signal is delayed by [7+ (# Channels Sampled)] cycles of the CONV_CLK after
a SYNC reset. This is due to the latency of the pipeline architecture of the THS1209.
Sampling Rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1
shows the maximum conversion rate for different combinations.
Table 1. Maximum Conversion Rate
CHANNEL CONFIGURATION
1 single-ended channel
2 single-ended channels
1 differential channel
NUMBER OF CHANNELS
1
2
1
MAXIMUM CONVERSION
RATE PER CHANNEL
8 MSPS
4 MSPS
8 MSPS
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:
fc
+
8 MSPS
# channels
14