SM73301 Datasheet, PDF (15/22 Pages) Texas Instruments – RRIO, High Output Current & Unlimited Cap Load Op Amp in SOT23-5

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BLOCK DIAGRAM AND OPERATIONAL DESCRIPTION
A) Input Stage
FIGURE 1. Simplified Schematic Diagram
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As can be seen from the simplified schematic in Figure 1, the
input stage consists of two distinct differential pairs (Q1-Q2
and Q3-Q4) in order to accommodate the full Rail-to-Rail input
common mode voltage range. The voltage drop across R5,
R6, R7, and R8 is kept to less than 200mV in order to allow
the input to exceed the supply rails. Q13 acts as a switch to
steer current away from Q3-Q4 and into Q1-Q2, as the input
increases beyond 1.4V of V⁺. This in turn shifts the signal path
from the bottom stage differential pair to the top one and
causes a subsequent increase in the supply current.
In transitioning from one stage to another, certain input stage
parameters (V_OS, I_b, I_OS, e_n, and i_n) are determined based on
which differential pair is "on" at the time. Input Bias current,
I_B, will change in value and polarity as the input crosses the
transition region. In addition, parameters such as PSRR and
CMRR which involve the input offset voltage will also be ef-
fected by changes in V_CM across the differential pair transition
region.
The input stage is protected with the combination of R9-R10
and D1, D2, D3, and D4 against differential input over-volt-
ages. This fault condition could otherwise harm the differential
pairs or cause offset voltage shift in case of prolonged over
voltage. As shown in Figure 2, if this voltage reaches approx-
imately ±1.4V at 25°C, the diodes turn on and current flow is
limited by the internal series resistors (R9 and R10). The Ab-
solute Maximum Rating of ±10V differential on V_IN still needs
to be observed. With temperature variation, the point were the
diodes turn on will change at the rate of 5mV/°C.
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