OPA354AIDBVRG4 Datasheet, PDF (15/32 Pages) Texas Instruments – 250MHz, Rail-to-Rail I/O, CMOS OPERATIONAL AMPLIFIERS

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The key elements to a transimpedance design, as shown
in Figure 8, are the expected diode capacitance (including
the parasitic input common-mode and differential-mode
input capacitance (2 + 2)pF for the OPA354), the desired
transimpedance gain (R_F), and the Gain-Bandwidth
Product (GBW) for the OPA354 (100MHz). With these 3
variables set, the feedback capacitor value (C_F) may be set
to control the frequency response.
C_F
< 1pF
(prevents gain peaking)
R_F
10MΩ
+V
λ
C_D OPA354
V_OUT
Figure 8. Transimpedance Amplifier
To achieve a maximally flat 2nd-order Butterworth
frequency response, the feedback pole should be set to:
Ǹ ¹
2pR_FC_F
+
GBP
4pR_FC_D
(1)
Typical surface-mount resistors have a parasitic
capacitance of around 0.2pF that must be deducted from
the calculated feedback capacitance value.
Bandwidth is calculated by:
Ǹ f_*3dB +
GBP
2pR_FC
D
Hz
(2)
For even higher transimpedance bandwidth, the
high-speed CMOS OPA355 (200MHz GBW) or the
OPA655 (400MHz GBW) may be used.
PCB LAYOUT
Good high-frequency printed circuit board (PCB) layout
techniques should be employed for the OPA354.
Generous use of ground planes, short and direct signal
traces, and a suitable bypass capacitor located at the V+
pin will assure clean, stable operation. Large areas of
copper also provides a means of dissipating heat that is
generated in normal operation.
Sockets are definitely not recommended for use with any
high-speed amplifier.
OPA354
OPA2354
OPA4354
SBOS233E − MARCH 2002− REVISED MAY 2009
A 10nF ceramic bypass capacitor is the minimum
recommended value; adding a 1µF or larger tantalum
capacitor in parallel can be beneficial when driving a
low-resistance load. Providing adequate bypass
capacitance is essential to achieving very low harmonic
and intermodulation distortion.
POWER DISSIPATION
Power dissipation depends on power-supply voltage,
signal and load conditions. With DC signals, power
dissipation is equal to the product of output current times
the voltage across the conducting output transistor,
V_S − V_O. Power dissipation can be minimized by using the
lowest possible power-supply voltage necessary to assure
the required output voltage swing.
For resistive loads, the maximum power dissipation occurs
at a DC output voltage of one-half the power-supply
voltage. Dissipation with AC signals is lower. Application
Bulletin AB-039 (SBOA022), Power Amplifier Stress and
Power Handling Limitations, explains how to calculate or
measure power dissipation with unusual signals and
loads, and can be found at www.ti.com.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature
should be limited to 150°C, maximum. To estimate the
margin of safety in a complete design, increase the
ambient temperature until the thermal protection is
triggered at 160°C. The thermal protection should trigger
more than 35°C above the maximum expected ambient
condition of your application.
PowerPAD THERMALLY ENHANCED
PACKAGE
Besides the regular SOT23-5 and MSOP-8, the single and
dual versions of the OPA354 also come in SO-8
PowerPAD. The SO-8 PowerPAD is a standard-size SO-8
package where the exposed leadframe on the bottom of
the package can be soldered directly to the PCB to create
an extremely low thermal resistance. This will enhance the
OPA354’s power dissipation capability significantly and
eliminates the use of bulky heatsinks and slugs
traditionally used in thermal packages. This package can
be easily mounted using standard PCB assembly
techniques. NOTE: Since the SO-8 PowerPAD is
pin-compatible with standard SO-8 packages, the
OPA354 and OPA2354 can directly replace operational
amplifiers in existing sockets. Soldering the PowerPAD to
the PCB is always required, even with applications that
have low power dissipation. This provides the necessary
thermal and mechanical connection between the
leadframe die pad and the PCB.
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