OPA2652 Datasheet, PDF (15/23 Pages) Burr-Brown (TI) – Dual, 700MHz, Voltage-Feedback OPERATIONAL AMPLIFIER

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E_NI
R_S
I_BN
1/2
OPA2652
E_O
E_RS
4kTR_S
4kT
R_G
R_F
4kTR_F
R_G
I_BI
4kT = 1.6 x 10^-20J
at 290°K
Figure 35. Op Amp Noise Analysis Model
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 1 shows the
general form for the output noise voltage using the
terms shown in Figure 35.
Ǹ ǒ Ǔ _{EN +}
2
E_NI2)ǒI
BN^RS^Ǔ
2
)4kTR_S)
I _BIR _F
NG
)
4kTR
NG
F
(1)
Dividing this expression by the noise gain (NG = 1 +
R_F/R_G) gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 2.
Ǹǒ Ǔ E_O +
E_NI2)ǒI_BNR_S^Ǔ2)4kTR_S NG²)(I_BIR_F)²)4kTR_FNG
(2)
Evaluating these two equations for the OPA2652
circuit and component values shown in Figure 28
gives a total output spot noise voltage of 17nV/√Hz
and a total equivalent input spot noise voltage of
8.4nV/√Hz. This noise includes the noise added by
the bias current cancellation resistor (205Ω) on the
noninverting input. This total input-referred spot
noise voltage is only slightly higher than the 8nV/√Hz
specification for the op amp voltage noise alone.
This result will be the case as long as the
impedances appearing at each op amp input are
limited to the previously recommend maximum value
of 300Ω. Keeping both (R_F || R_G) and the
noninverting input source impedance less than 300Ω
satisfies both noise and frequency response flatness
considerations. Since the resistor-induced noise is
relatively negligible, additional capacitive decoupling
across the bias current cancellation resistor (R_B) for
the inverting op amp configuration of Figure 29 is not
required.
OPA2652
SBOS125A – JUNE 2000 – REVISED MAY 2006
DC Accuracy and Offset Control
The balanced input stage of a wideband voltage
feedback op amp allows good output DC accuracy in
a wide variety of applications. Although the
high-speed input stage does require relatively high
input bias current (typically 4µA out of each input
terminal), the close matching between them may be
used to significantly reduce the output DC error
caused by this current. This reduction is done by
matching the DC source resistances appearing at the
two inputs. This matching reduces the output DC
error resulting from the input bias currents to the
offset current times the feedback resistor. Evaluating
the configuration of Figure 28, using worst-case
+25°C input offset voltage and current specifications,
gives a worst-case output offset voltage equal to:
ǒ Ǔ ǒ Ǔ _{" NG @ VOS(MAX) " RF @ IOS(MAX)}
+ " (1.94 @ 7.0mV) " (402W @ 1.0mA)
+ " 14.0mV
ǒ_{NG + noninverting signal gain}Ǔ
A fine scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques
are available for introducing DC offset control into an
op amp circuit. Most of these techniques add a DC
current through the feedback resistor. In selecting an
offset trim method, one key consideration is the
impact on the desired signal path frequency
response. If the signal path is intended to be
noninverting, the offset control is best applied as an
inverting summing signal to avoid interaction with the
signal source. If the signal path is intended to be
inverting, applying the offset control to the
noninverting input may be considered. However, the
DC offset voltage on the summing junction sets up a
DC current back into the source which must be
considered. Applying an offset adjustment to the
inverting op amp input can change the noise gain
and frequency response flatness. For a DC-coupled
inverting amplifier, Figure 36 shows one example of
an offset adjustment technique that has minimal
impact on the signal frequency response. In this
case, the DC offset current is brought into the
inverting input node through resistor values that are
much larger than the signal path resistors. This
configuration ensures that the adjustment circuit has
minimal effect on the loop gain, and therefore on the
frequency response as well.
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