OPA2634 Datasheet, PDF (15/17 Pages) Burr-Brown (TI) – Dual, Wideband, Single-Supply OPERATIONAL AMPLIFIER

DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage-feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power-supply current trim for the OPA2634
gives even tighter control than comparable products. Al-
though the high-speed input stage does require relatively
high input bias current (typically 25µA out of each input
terminal), the close matching between them may be used to
reduce the output DC error caused by this current. This is
done by matching the DC source resistances appearing at the
two inputs. Evaluating the configuration of Figure 1 (which
has matched DC input resistances), using worst-case +25°C
input offset voltage and current specifications, gives a worst-
case output offset voltage equal to (NG = non-inverting
signal gain at DC):
±(NG • V_OS(MAX)) ± (R_F • I_OS(MAX))
= ±(1 • 7.0mV) ± (750Ω • 2.25µA)
= ±8.7mV [Output Offset Range for Figure 1]
A fine scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp
circuit. Most of these techniques are based on adding a DC
current through the feedback resistor. In selecting an offset
trim method, one key consideration is the impact on the
desired signal path frequency response. If the signal path is
intended to be non-inverting, the offset control is best
applied as an inverting summing signal to avoid interaction
with the signal source. If the signal path is intended to be
inverting, applying the offset control to the non-inverting
input may be considered. Bring the DC offsetting current
into the inverting input node through resistor values that are
much larger than the signal path resistors. This will insure
that the adjustment circuit has minimal effect on the loop
gain and hence the frequency response.
THERMAL ANALYSIS
Maximum desired junction temperature will set the maxi-
mum allowed internal power dissipation as described below.
In no case should the maximum junction temperature be
allowed to exceed 175°C.
Operating junction temperature (T_J) is given by T_A + P_D•θ_JA.
The total internal power dissipation (P_D) is the sum of
quiescent power (P_DQ) and additional power dissipated in the
output stage (P_DL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P_DL will depend on the
required output signal and load but would, for resistive load
connected to mid-supply (V_S/2), be at a maximum when the
output is fixed at a voltage equal to V_S/4 or 3V_S/4. Under this
condition, P_DL = V_S2/(16 • R_L), where R_L includes feedback
network loading.
Note that it is the power in the output stage, and not into the
load, that determines internal power dissipation.
As a worst-case example, compute the maximum T_J using
the circuit of Figure 1 operating at the maximum specified
ambient temperature of +85°C and driving a 150Ω load at
mid-supply, for both channels:
P_D = 2 (10V • 13.5mA + 5²/(16 • (150Ω || 1500Ω))) = 289mW
Maximum T_J = +85°C + (0.29W • 125°C/W) = 121°C
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower guaranteed junction temperatures. The highest
possible internal dissipation will occur if the load requires
current to be forced into the output at high output voltages
or sourced from the output at low output voltages. This puts
a high current through a large internal voltage drop in the
output transistors.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA2634 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance
to cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. Each power-supply
connection should always be decoupled with one of these
capacitors. An optional supply decoupling capacitor (0.1µF)
across the two power supplies (for bipolar operation) will
improve 2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower fre-
quency, should also be used on the main supply pins. These
may be placed somewhat farther from the device and may be
shared among several devices in the same area of the PC
board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance.
Resistors should be a very low reactance type. Surface-
mount resistors work best and allow a tighter overall layout.
Metal film or carbon composition axially-leaded resistors
can also provide good high-frequency performance. Again,
OPA2634
15
SBOS098A