MSP430F11X_14 Datasheet, PDF (15/34 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F11x
MIXED SIGNAL MICROCONTROLLER
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
outputs Port 1 to Port 2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
High-level output voltage
VOH _{Port 1}
I(OHmax) = −1.5 mA
I(OHmax) = −6 mA
I(OHmax) = −1.5 mA
I(OHmax) = −6 mA
VCC = 2.2 V
VCC = 3 V
See Note 1
See Note 2
See Note 1
See Note 2
VCC−0.25
VCC−0.6
VCC−0.25
VCC−0.6
VCC
VCC
V
VCC
VCC
High-level output voltage
VOH _{Port 2}
I(OHmax) = −1 mA
I(OHmax) = −3.4 mA
I(OHmax) = −1 mA
I(OHmax) = −3.4 mA
VCC = 2.2 V
VCC = 3 V
See Note 3
See Note 3
See Note 3
See Note 3
VCC−0.25
VCC−0.6
VCC−0.25
VCC−0.6
VCC
VCC
V
VCC
VCC
Low-level output voltage
VOL _{Port 1 and Port 2}
I(OLmax) = 1.5 mA
I(OLmax) = 6 mA
I(OLmax) = 1.5 mA
I(OLmax) = 6 mA
VCC = 2.2 V
VCC = 3 V
See Note 1
See Note 2
See Note 1
See Note 2
VSS
VSS
VSS
VSS
VSS+0.25
VSS+0.6
V
VSS+0.25
VSS+0.6
NOTES:
1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage
drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
3. One output loaded at a time.
outputs P1.x, P2.x, TAx
PARAMETER
f(P20)
Output frequency
f(TAx)
TEST CONDITIONS
P2.0/ACLK, CL = 20 pF
TA0, TA1, TA2, CL = 20 pF
Internal clock source, SMCLK signal applied
(See Note 1)
VCC
2.2 V/3 V
MIN TYP MAX
fSystem
2.2 V/3 V
dc
fSystem
P1.4/SMCLK, CL = 20 pF
fSMCLK = fLFXT1 = fXT1
fSMCLK = fLFXT1 = fLF
fSMCLK = fLFXT1/n
2.2 V/3 V
40%
35%
50%−
15 ns
50%
60%
65%
50%+
15 ns
t(Xdc) Duty cycle of O/P
frequency
fSMCLK = fDCOCLK
2.2 V/3 V
50%−
15 ns
50%
fP20 = fLFXT1 = fXT1
40%
P2.0/ACLK, CL = 20 pF
fP20 = fLFXT1 = fLF
fP20 = fLFXT1/n
2.2 V/3 V
30%
50%
t(TAdc)
TA0, TA1, TA2, CL = 20 pF, Duty cycle = 50%
2.2 V/3 V
0
NOTE 1: The limits of the system clock MCLK have to be met. MCLK and SMCLK can have different frequencies.
50%+
15 ns
60%
70%
±50
UNIT
MHz
ns
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