LMK61E0M Datasheet, PDF (15/47 Pages) Texas Instruments – Ultra-Low Jitter Programmable Oscillator with Internal EEPROM

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LMK61E0M
SNAS692 – JANUARY 2017
Device Functional Modes (continued)
8.4.2.2 Fine Frequency Margining
IEEE802.3 dictates that Ethernet frames stay compliant to the standard specifications when clocked with a
reference clock that is within ±100 ppm of its nominal frequency. In the worst case, an RX node with its local
reference clock at –100 ppm from its nominal frequency should be able to work seamlessly with a TX node that
has its own local reference clock at +100 ppm from its nominal frequency. Without any clock compensation on
the RX node, the read pointer will severely lag behind the write pointer and cause FIFO overflow errors. On the
contrary, when the RX node’s local clock operates at +100 ppm from its nominal frequency and the TX node’s
local clock operates at –100 ppm from its nominal frequency, FIFO underflow errors occur without any clock
compensation.
In order to prevent such overflow and underflow errors from occurring, modern ASICs and FPGAs include a clock
compensation scheme that introduces elastic buffers. Such a system, shown in Figure 7, is validated thoroughly
during the validation phase by interfacing slower nodes with faster ones and ensuring compliance to IEEE802.3.
The LMK61E0 provides the ability to fine tune the frequency of its outputs based on changing its load
capacitance for the integrated oscillator. This fine tuning can be done via I²C as described in Integrated
Oscillator. The change in load capacitance is implemented in a manner such that the output of LMK61E0
undergoes a smooth monotonic change in frequency.
8.4.2.3 Coarse Frequency Margining
Certain systems require the processors to be tested at clock frequencies that are slower or faster by 5% or 10%.
The LMK61E0 offers the ability to change its output divider for the desired change from its nominal output
frequency as explained in High-Speed Output Divider.
TX
RX
Serializer
Parallel
Data
TX PLL
+/- 100 ppm
Ref Clk
Serialized clock/data
Sampler
Recovered
Clock
Parallel
Data
CDR
Deserializer
Post Processing
w/ clock
compensation
+/- 100 ppm
Ref Clk
Elastic Buffer
(clock compensation)
FIFO
circular
Latency
Write
Pointer
Read
Pointer
Figure 7. System Implementation with Clock Compensation for Standards Compliance
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