LMK61E0M Datasheet, PDF (1/47 Pages) Texas Instruments – Ultra-Low Jitter Programmable Oscillator with Internal EEPROM

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LMK61E0M
SNAS692 – JANUARY 2017
LMK61E0M Ultra-Low Jitter Programmable Oscillator with Internal EEPROM
1 Features
•1 Ultra-Low Noise, High Performance
– Jitter: 500 fs RMS Typical f_OUT > 50 MHz on
LMK61E0M
• LMK61E0M supports 3.3-V LVCMOS output up to
200 MHz
• Total Frequency Tolerance of ±25 ppm
• System Level Features
– Glitch-less Frequency Margining: Up to ±1000
ppm from nominal
– Internal EEPROM: User configurable startup
settings
• Other Features
– Device Control: Fast Mode I²C up to 1000 kHz
– 3.3-V Operating Voltage
– Industrial Temperature Range (–40ºC to
+85ºC)
– 7-mm x 5-mm 8-Pin Package
• Default Frequency 70.656 MHz
3 Description
The LMK61E0 family of ultra-low jitter PLLatinum^TM
programmable oscillators utilize fractional-N
frequency synthesizers with integrated VCOs to
generate commonly used reference clocks. The
LMK61E0M supports 3.3-V LVCMOS outputs. The
device features self startup from on-chip EEPROM to
generate a factory programmed default output
frequency, or the device registers and EEPROM
settings are fully programmable in-system via I²C
serial interface. The device provides fine and coarse
frequency margining control via I²C serial interface,
making it a digitally controlled oscillator (DCXO).
The PLL feedback divider can be updated to adjust
the output frequency without spikes or glitches in
steps of <1ppb using a PFD of 12.5MHz (R divider=4,
doubler disabled) for compatibility with xDSL
requirements, or in steps of <5.2ppb using a PFD of
100MHz (R divider=1, doubler enabled) for
compatibility with broadcast video requirements. The
frequency margining features also facilitate system
design verification tests (DVT), such as standards
compliance and system timing margin testing.
2 Applications
• High-Performance Replacement for Crystal, SAW,
or Silicon-Based Oscillators
• Switches, Routers, Network Line Cards, Base
Band Units (BBU), Servers, Storage/SAN
• Test and Measurement
• Medical Imaging
• FPGA, Processor Attach
• xDSL, Broadcast Video
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMK61E0M
QFM (SIA) (8)
7.00 mm x 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Pinout and Simplified Block Diagram
OE 1
SDA
7
6 VDD
ADD 2
5 OUTN
GND 3
8
SCL
4 OUTP
Integrated
Oscillator
Power
Conditioning
Output
Output
PLL
Divider
Buffer
LMK61E0X
Ultra-high performance oscillator
Interface
I²C/EEPROM
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.