CLC021_14 Datasheet, PDF (15/25 Pages) Texas Instruments – SMPTE 259M Digital Video Serializer with EDH Generation and Insertion

CLC021
www.ti.com
SNLS068H – MAY 2000 – REVISED APRIL 2013
APPLICATION INFORMATION
A typical application circuit for the CLC021 is shown in Figure 9. This circuit demonstrates the capabilities of the
CLC021 and allows its evaluation in a variety of configurations. Assembled demonstration boards with more
comprehensive evaluation options are available, part number SD021-5EVK (5V device) or SD021-3EVK (3.3V
device). The boards may be ordered through any of Texas Instruments' sales offices. Complete circuit board
layouts and schematics including Gerber photoplot files, for the demonstration boards are available on Texas
Instruments' website in the application information for this device.
APPLICATION CIRCUIT
Figure 9. Typical Application Circuit
The SD021EVK application circuit boards, Figure 10, can accommodate different input and output drive and
loading options. Pin headers are provided for input and control I/O signal access. Install the appropriate value
resistor packs, 220Ω at RP1 and RP3 and 330Ω at RP2 and RP4, for TTL cabled interfaces before applying
input signals. Install 51Ω resistor packs at RP2 and RP4 for signal sources requiring such loading. Remove any
resistor packs at RP1 and RP3 when using 50Ω source loading.
The board's outputs may be DC interfaced to PECL inputs by first installing 124Ω resistors at R1B and R2B,
changing R1A and R2A to 187Ω and replacing C1 and C2 with short circuits. The PECL inputs should be directly
connected to J1 and J2 without cabling. If 75Ω cabling is used to connect the CLC021 to the PECL inputs, the
voltage dividers used on the CLC021 outputs must be removed and re-installed on the circuit board where the
PECL device is mounted. This will provide correct termination for the cable and biasing for both the CLC021's
outputs and the PECL inputs. It is most important to note that a 75Ω or equivalent DC loading (measured with
respect to the negative supply rail) must always be installed at both of the CLC021's SDO outputs to obtain
proper signal levels from device. When using 75Ω Thevenin-equivalent load circuits, the DC bias applied to the
SDO outputs should not exceed +3V (+1.3V for CLC021AVGZ-3.3) with respect to the negative supply rail. Serial
output levels should be reduced to 400 mV_p-p by changing R_REF to 3.4 kΩ. This may be done by removing the
Output Level shorting jumper on the post header.
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Product Folder Links: CLC021
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