CLC021_14 Datasheet, PDF (14/25 Pages) Texas Instruments – SMPTE 259M Digital Video Serializer with EDH Generation and Insertion

CLC021
SNLS068H – MAY 2000 – REVISED APRIL 2013
Pin
Name
1
Reset
2
NRZ-NRZI
3
Test Out
4
V_SS
5
V_SS
6
V_DD
7
V_DD
8
EDH Force
9
EDH Enable
10
SMPTE Mode
11
N/C
12
D0
13
D1
14
D2
15
D3
16
D4
17
D5
18
D6
19
D7
20
D8
21
D9
22
P_CLK
23
H/Line-Field b0 (LSB)
24
V/Line-Field b1
25
F/Line-Field b2 (MSB)
26
Lock Detect
27
V_SSO
28
V_DDO
29
TPG Enable
30
V_SSOD
31
V_SSOD
32
V_DDOD
33
V_DDOD
34
N/C
35
R_REF
36
V_DDOD
37
V_SSSD
38
SDO
39
SDO
40
V_DDSD
41
Sync Detect Enable
42
NSP
43
ANC
44
NTSC/PAL
PIN DESCRIPTIONS⁽¹⁾
Description
Manual Reset Input (High True)
NRZ-to-NRZI Conversion Control (NRZ=High, NRZI=Low)
Test Out (BIST Pass/Fail Indicator)
Negative Power Supply Input (Digital Logic)
Negative Power Supply Input (Digital Logic)
Positive Power Supply Input (Digital Logic)
Positive Power Supply Input (Digital Logic)
Force Insertion of New EDH and Flags in Serial Output Data (High True)
EDH Enable Input (Low True)
SMPTE/non-SMPTE Mode Select Input (SMPTE Mode=Low)
No Connect
Parallel Data Input (Internal Pull-Down to V_SS)
Parallel Data Input (Internal Pull-Down to V_SS)
Parallel Data Input (Internal Pull-Down to V_SS)
Parallel Data Input (Internal Pull-Down to V_SS)
Parallel Data Input (Internal Pull-Down to V_SS)
Parallel Data Input (Internal Pull-Down to V_SS)
Parallel Data Input (Internal Pull-Down to V_SS)
Parallel Data Input (Internal Pull-Down to V_SS)
Parallel Data Input (Internal Pull-Down to V_SS)
Parallel Data Input (Internal Pull-Down to V_SS)
Parallel Clock Input (Internal Pull-Down to V_SS)
H-Bit Output (Component); Line-Field ID (Composite)
V-Bit Output (Component); Line-Field ID (Composite)
F-Bit Output (Component); Line-Field ID (Composite)
Lock Detector Output (High True)
Negative Power Supply Input (PLL Supply)
Positive Power Supply Input (PLL Supply)
TPG Enable (High True)
Negative Power Supply Input (PLL Digital Supply)
Negative Power Supply Input (PLL Digital Supply)
Positive Power Supply Input (PLL Digital Supply)
Positive Power Supply Input (PLL Digital Supply)
No Connect
Output Level Reference Resistor (1.69 kΩ, 1% Nominal Value)
Positive Power Supply Input (PLL Digital Supply)
Negative Power Supply Input (Output Driver)
Serial Data True Output
Serial Data Complement Output
Positive Power Supply Input (Output Driver)
Parallel Data Sync Detection Enable Input (Low True)
New Sync Position Output
Ancilliary Data Header Flag Output
NTSC/PAL Mode Indicator Output (PAL=High, NTSC=Low)
(1) All CMOS/TTL inputs have internal pull-down devices.
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