BQ4845_14 Datasheet, PDF (15/24 Pages) Texas Instruments – Parallel RTC With CPU Supervisor

Write Cycle No. 1 (WE-Controlled) ^1,2,3
bq4845/bq4845Y
Write Cycle No. 2 (CS-Controlled) ^1,2,3,4,5
Notes:
Aug. 1995
1. CS or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
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