BQ4845_14 Datasheet, PDF (13/24 Pages) Texas Instruments – Parallel RTC With CPU Supervisor

bq4845/bq4845Y
Read Cycle (TA = TOPR, _VCCmin ≤ VCC ≤ VCCmax)
Symbol
Parameter
tRC
Read cycle time
tAA
Address access time
tACS
Chip select access time
tOE
Output enable to output valid
tCLZ
Chip select to output in low Z
tOLZ
Output enable to output in low Z
tCHZ
Chip deselect to output in high Z
tOHZ
Output disable to output in high Z
tOH
Output hold from address change
Min.
70
-
-
-
5
0
0
0
10
Max.
-
70
70
35
-
-
25
25
-
Unit
Conditions
ns
ns Output load A
ns Output load A
ns Output load A
ns Output load B
ns Output load B
ns Output load B
ns Output load B
ns Output load A
Write Cycle (TA =TOPR _{, VCCmin} ≤ VCC ≤ VCCmax)
Symbol
tWC
tCW
tAW
Parameter
Write cycle time
Chip select to end of write
Address valid to end of write
tAS
Address setup time
tWP
Write pulse width
tWR1
Write recovery time (write cycle 1)
tWR2
Write recovery time (write cycle 2)
tDW
Data valid to end of write
tDH1
Data hold time (write cycle 1)
tDH2
tWZ
tOW
Data hold time (write cycle 2)
Write enabled to output in high Z
Output active from end of write
Min. Max. Unit
Conditions
70
-
ns
65
-
ns
(1)
65
-
ns
(1)
Measured from address valid to beginning
0
-
ns _{of write. (2)}
Measured from beginning of write to end of
55
-
ns _{write. (1)}
Measured from WE going high to end of
5
-
ns _{write cycle. (3)}
Measured from CS going high to end of
15
-
ns _{write cycle. (3)}
Measured to first low-to-high transition of
30
-
ns _{either CS or WE.}
Measured from WE going high to end of
0
-
ns _{write cycle. (4)}
Measured from CS going high to end of
10
-
ns _{write cycle. (4)}
0 25 ns I/O pins are in output state. (5)
0
-
ns I/O pins are in output state. (5)
Notes: 1. A write ends at the earlier transition of CS going high and WE going high.
2. A write occurs during the overlap of a low CS and a low WE. A write begins at the later transition
of CS going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Aug. 1995
13