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BQ24700_14 Datasheet, PDF (15/32 Pages) Texas Instruments – NOTEBOOK PC BATTERY CHARGE CONTROLLER
ą
bq24700, bq24701
NOTEBOOK PC BATTERY CHARGE CONTROLLER
AND SELECTOR WITH DPM
SLUS452B – APRIL 2001 – REVISED NOVEMBER 2002
APPLICATION INFORMATION
+
ISW
SW
VADPT
VBAT
COMP
10
ZCOMP
CLK
OSC
RAMP
5V
100 µA
ENABLE
LATCH OUT
SQ
RQ
PWM COMPARATOR
FROM ENABLE LOGIC
LEVEL
SHIFT
VCC
PWM
DRIVE
VHSP
21
PWM
ENABLE
+
BATTERY
VOLTAGE
BATTERY CHARGE
CURRENT
ADP CURRENT
gm
AMPLIFIERS
+
1.25 V
13
BATP
Figure 3. PWM Controller Block Diagram
UDG–00114
PWM operation
The three open collector gm amplifiers are tied to the COMP pin (refer to Figure 3), which is internally biased
up by a 100-µA constant current source. The voltage on the COMP pin is the control voltage (VC) for the PWM
comparator. The PWM comparator compares VC to the sawtooth ramp of the internally fixed 300-kHz oscillator
to provide duty cycle information for the PWM drive. The PWM drive is level-shifted to provide adequate gate
voltage levels for the external P-channel MOSFET. Refer to PWM selector switch gate drive section for gate
drive voltage levels.
softstart
Softstart is provided to ensure an orderly start-up when the PWM is enabled. When the PWM controller is
disabled (ENABLE = Low), the 100-µA current source pullup is disabled and the COMP pin is actively pulled
down to GND. Disabling the 100-µA pullup reduces current drain when the PWM is disabled. When the
bq24700/bq24701 PWM is enabled (ENABLE = High), the COMP pin is released and the 100-µA pullup is
enabled (refer to Figure 3). The voltage on the COMP pin increases as the pullup charges the external
compensation network connected to the COMP pin. As the voltage on the COMP pin increases the PWM duty
cycle increases linearly as shown in Figure 4.
NOTE:The ENABLE pin should be asserted high only after ACDET has been asserted high and
VREF has been established. When ac is lost, and the bq24700/bq24701 drives ACPRES low, the
host must assert the ENABLE low.
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