ADC122S625_15 Datasheet, PDF (15/28 Pages) Texas Instruments – Dual 12-Bit, 50 kSPS to 200 kSPS, Simultaneous Sampling A/D Converter

ADC122S625
www.ti.com
SNAS451A – FEBRUARY 2008 – REVISED MARCH 2013
ANALOG SIGNAL INPUTS
The ADC122S625 has dual differential inputs where the effective input voltage that is digitized is CHA+ minus
CHA− (DIFFINA) and CHB+ minus CHB− (DIFFINB). As is the case with all differential input A/D converters,
operation with a fully differential input signal or voltage will provide better performance than with a single-ended
input. However, the ADC122S625 can be presented with a single-ended input as shown in Single-Ended Input
Operation and the Application Circuits.
The current required to recharge the input sampling capacitor will cause voltage spikes at the + and − inputs. Do
not try to filter out these noise spikes. Rather, ensure that the noise spikes settle out during the acquisition period
(three SCLK cycles after the fall of CS). This is true for both Channel A and Channel B since both channels are
converted simultaneously on the fourth falling edge of SCLK after CS is asserted.
Differential Input Operation
With a fully differential input voltage or signal, a positive full scale output code (0111 1111 1111b or 7FFh) will be
obtained when DIFFINA or DIFFINB is greater than or equal to V_REF − 1.5 LSB. A negative full scale code (1000
0000 0000b or 800h) will be obtained when DIFFINA or DIFFINB is greater than or equal to −V_REF + 0.5 LSB.
This ignores gain, offset and linearity errors, which will affect the exact differential input voltage that will
determine any given output code. Figure 34 shows the ADC122S625 being driven by a full-scale differential
source.
SRC
VCM
+
VREF
2
VCM
VCM -
VREF
2
RS
CS
RS
VCM
+
VREF
2
VCM
VCM -
VREF
2
+
ADC122S625
-
Figure 34. Differential Input
Single-Ended Input Operation
For single-ended operation, the non-inverting inputs of the ADC122S625 can be driven with a signal that has a
maximum to minimum value range that is equal to or less than twice the reference voltage. The inverting inputs
should be biased at a stable voltage that is halfway between these maximum and minimum values. In order to
utilize the entire dynamic range of the ADC122S625, the reference voltage is limited at V_A / 2. This allows the
non-inverting inputs the maximum swing range of ground to V_A. Figure 35 shows the ADC122S625 being driven
by a full-scale single-ended source. Even though the design of the ADC122S625 is optimized for a differential
input, there is very little performance degradation while operating the ADC122S625 in single-ended fashion.
SRC
VCM + VREF
VCM
VCM - VREF
RS
CS
+
ADC122S625
-
VCM
Figure 35. Single-Ended Input
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